SLA60000.PDF

(10 KB) Pobierz
Preliminary
EPSON
SLA60000 Series
High Speed Gate Array
0.25um CMOS Gate Array
Low power consumption
Covered from 99k to 2,519k raw gates
DESCRIPTION
The SLA60000 Series are CMOS Gate Arrays which are adopting on 0.25um silicon gate process
with 3 and 4-metal layers. There are 10 arrays which are covering from 98,892 to 2,588,040 raw gate
for immediate applications to large scale and high speed systems.
FEATURES
Adopting on 0.25um CMOS silicon gate with 3 and 4 metal layers
10 arrays covered with 98,892 to 2,588,040 gates
2.5V single power supply or 2.5/3.3V dual power supply operation
56ps propagation delay at 2.5V - 2 input NAND gate, F/O=1, Typical
Low power consumption - 0.17uW/BC/MHz at 2.5V, F/O=1
Input / Output Level - CMOS, LVTTL, Schmitt, PCI, LVDS*
?
Output drive ability - I
OL
=0.1 / 1 / 3 / 8 / 12 / 24mA at HV
DD
=3.3V, LV
DD
=2.5V
?
SRAM, ROM, Flash and various function cells are available
*Planning
PRODUCT LINEUP - Planning
Master
TotalBC(Rawgates)
Usable
BC
4LM
number of
PAD
70um
Internal
Delay
Input
Output
I/OLevel
InputMode
OutputMode
tpd = 270ps (2.5V, F/O=2, Typical)
tpd = 1600ps (2.5V, CL = 15pF, Typical)
CMOS, LVTTL, PCI3.3V, LVDS*
Normal, Pull-up/Pull down, Schmitt, level shifter, Fail-safe*, Gated*
Normal, Open drain, 3-state, Bi-directional, Level shifter, Fail-safe*, Gated*
*Planning
112
148
188
224
272
(320)
(388)
(440)
(480)
(552)
80um
89,298
(104)
154,548
(132)
241,735
(168)
340,247
(200)
506,058
(240)
665,258
284
987,856
344
1,270,203
388
1,427,220
424
1,889,703
488
3LM
SLA6009
99,200
79,376
SLA6017
171,720
137,376
SLA6028
284,394
199,076
SLA6040
400,290
280,203
SLA6059
595,362
416,753
SLA6083
831,572
540,522
SLA6123*
1,234,820
802,633
SLA6158*
1,587,754
1,032,040
SLA6190*
1,902,960
1,141,776
SLA6251*
2,519,604
1,511,762
tpd = 56ps (2 input NAND gate, 2.5V, Typical)
SEIKO EPSON CORPORATION

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin