DA0R22MB6D1 Rev D HP G6-1129ER Quanta - EC KB3930QF A1.pdf

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8
R22 SYSTEM DIAGRAM
DDR3-SODIMM1
PAGE 6
A
01
A
DDR3 channel A
AMD Champlain
35mm X 35mm
DDR3 channel B
CPU THERMAL
SENSOR
PAGE 5
DDR3-SODIMM2
PAGE 7
S1G4 Processor
638P (PGA)35W/25W
PAGE 3,4,5
HT3
PCI-Express 8X
PCI-E
X1
Flash Media
RTS5219-GR
PAGE 26
B
X1
X1
Mini PCI-E
Card
(Wireless LAN)
NORTH BRIDGE
RS880M A12
21mm X 21mm, 528pin BGA
Side port
HDMI
PAGE 25
CRT
PAGE 24
LVDS
PAGE 23
DDR3
LAN
Realtek
PCIE-LAN
(10/100)
RTS8165EH-CG
ATI
SEYMOUR-XT
23mm X 23mm
PAGE 17,18,19
20,21
B
PAGE 30
PAGE 33
PAGE 8,9,10,11
RJ45
PAGE 30
SYSTEM CHARGER(ISL6251)
DDR3 RAM
for UMA only
VRAM
PAGE 22
ALINK X4
SATA0 150MB
PAGE 8
USB2.0
0,5,8
PAGE 40
SYSTEM POWER ISL6237
15
BT softbreeze
PAGE 29
2
10
PCI-E WLAN Card x1
PAGE 33
SATA - HDD
PAGE 29
SATA - CD-ROM
SOUTH BRIDGE
SATA4 150MB
USB2.0 Ports
PAGE 29
X3
Webcam
X1
PAGE 23
PAGE 34
DDR II SMDDR_VTERM
1.8V/1.8VSUS(RT8207)
C
SB820 A13
21mm X 21mm, 605pin FCBGA
PAGE 29
PAGE 37
4.5W(Ext)
4.3W(Int)
Azalia
C
VCCP +1.1V AND +1.2V(RT8204)
PAGE 12,13,14,15,16
IDT
92HD80
PAGE 35
LPC
VGACORE(1.1V~1.2V)Oz8118
PAGE 27
PAGE 38
ENE KBC
CPU CORE ISL6265HRTZ-T
KB3930 Qx
PAGE 32
DIG MIC
AUDIO CONN
(Phone/ MIC)
PAGE 36
SMBUS TABLE
SB--SCL0/SD0
D
PAGE 27
PAGE 28
Clock gen/Robson/TV tuner
/DDR2/DDR2 thermal/Accelerometer
+3V
Keyboard
Touch Pad
PAGE 31
PAGE 31
FAN
PAGE 28
SPI
PAGE 31
D
epress card
Wlan Card
+3VS5
+3VPCU
+3V
EC --SCL/SD
EC--SCL2/SD2
1
Battery charge/discharge
VGA thermal/system thermal
PROJECT : R22
Quanta Computer Inc.
Size
Custom
NB5/RD2
Document Number
Block Diagram
1
8
Rev
1A
of
43
Date: Wednesday, September 15, 2010 Sheet
2
3
4
5
6
7
5
4
3
2
1
02
D
D
Use internal CLK GEN
C
C
B
B
A
A
PROJECT : R22
Quanta Computer Inc.
Size
Custom
NB5/RD2
5
4
3
2
Document Number
Clock Generator
2
of
43
1
Rev
1A
Date: Wednesday, September 15, 2010 Sheet
5
4
3
2
1
PBY201209T-221Y-N
VLDT use 1.5A Max current
+1.1V
R174
+1.1V
R54
*0_6/S
C389
C385
C383
10U/6.3V_8
0.22U/6.3V_4
180P/50V_4
+1.1V_VLDT
+1.1V_VLDT
+1.1V_VLDT
+1.1V_VLDT
D1
D2
D3
D4
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
J3
J2
J5
K5
N1
P1
P3
P4
*0_6/S
+1.1V_VLDT_R
U19A
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
+1.1V_VLDT
+2.5V
+CPUVDDA
L31
C414
LS0805-100M-N
4.7U/6.3V_6
C386
4.7U/6.3V_6
W/S= 15 mil/20mil
CPU CLK
C319
C322
0.22U/25V_6 3300P/50V_4
12
12
CPUCLKP
CPUCLKN
CPUCLKP
CPUCLKN
+CPUVDDA
H_THRMDC
H_THRMDA
CPU_PWRGD
CPU_LDT_RST#
CPU_LDT_STOP#
CPU_LDT_REQ#_CPU
300_4
300_4
300_4
*300/F_4
R148
R149
R177
R147
H_THRMDC 5
H_THRMDA 5
03
D
Keep trace from resisor to CPU within 0.6"
keep trace from caps to CPU within 1.2"
HT LINK
+1.1V_VLDT_R
+1.1V_VLDT_R
+1.1V_VLDT_R
+1.1V_VLDT_R
10U/6.3V_8
0.22U/6.3V_4
180P/50V_4
10U/6.3V_8
C111
C126
C133
C548
CPUCLKIN
CPUCLKP
CPUCLKN
R150
C395
C394
169/F_4
CPUCLKIN#
+1.5V
250mA
F8
F9
A9
A8
B7
A7
F10
C6
AF4
AF5
AE6
R6
P6
F6
E6
Y6
AB6
U19D
VDDA1
VDDA2
CLKIN_H
CLKIN_L
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
SIC
SID
ALERT_L
HT_REF0
HT_REF1
VDD0_FB_H
VDD0_FB_L
VDD1_FB_H
VDD1_FB_L
DBRDY
TMS
TCK
TRST_L
TDI
TEST23
TEST18
TEST19
TEST25_H
TEST25_L
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
TEST9
TEST6
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
SOCKET_638_PIN
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
DBREQ_L
TDO
TEST28_H
TEST28_L
TEST17
TEST16
TEST15
TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
W9
Y9
H6
G6
E10
AE9
J7
H8
D7
E7
F7
C7
C3
K8
C4
C9
C8
CPUTEST29L
H18
H19
AA7
D5
C5
CPUTEST17
CPUTEST16
CPUTEST15
CPUTEST14
R163
*300/F_4
T45
T40
T26
T49
+1.1V_VLDT
C
D
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
Y1
W1
Y4
Y3
R2
R3
T5
R5
W/S= 15 mil/20mil
+CPUVDDA
+CPUVDDA
CPUCLKIN
CPUCLKIN#
CPU_LDT_RST#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_REQ#_CPU
CPU_SIC
CPU_SID
CPU_ALERT
VSS
RSVD11
SVC
SVD
M11
W18
A6
A4
CPU_SVC_R
CPU_SVD_R
3900P/25V_4
3900P/25V_4
8 HT_NB_CPU_CAD_H[15..0]
8 HT_NB_CPU_CAD_L[15..0]
8 HT_NB_CPU_CLK_H[1..0]
8 HT_NB_CPU_CLK_L[1..0]
8 HT_NB_CPU_CTL_H[1..0]
8 HT_NB_CPU_CTL_L[1..0]
8 HT_CPU_NB_CAD_H[15..0]
8 HT_CPU_NB_CAD_L[15..0]
8 HT_CPU_NB_CLK_H[1..0]
8 HT_CPU_NB_CLK_L[1..0]
C
HT_NB_CPU_CAD_H[15..0]
HT_NB_CPU_CAD_L[15..0]
HT_NB_CPU_CLK_H[1..0]
HT_NB_CPU_CLK_L[1..0]
HT_NB_CPU_CTL_H[1..0]
HT_NB_CPU_CTL_L[1..0]
HT_CPU_NB_CAD_H[15..0]
HT_CPU_NB_CAD_L[15..0]
HT_CPU_NB_CLK_H[1..0]
HT_CPU_NB_CLK_L[1..0]
HT_CPU_NB_CTL_H[1..0]
HT_CPU_NB_CTL_L[1..0]
8 HT_CPU_NB_CTL_H[1..0]
8 HT_CPU_NB_CTL_L[1..0]
HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15
HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1
HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
SOCKET_638_PIN
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15
HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1
HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1
12 CPU_LDT_RST#
12 CPU_PWRGD
10,12 CPU_LDT_STOP#
5
5
5
CPU_SIC
CPU_SID
CPU_ALERT
R81
R83
THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC
THERMDA
AF6
AC7
AA8
W7
W8
CPU_THERMTRIP_L#
CPU_PROCHOT_L#
CPU_MEMHOT_L#
H_THRMDC
H_THRMDA
T10
SideBand Temp sense I2C
+1.5VSUS
+1.1V_VLDT
44.2/F_4
CPU_HTREF0
CPU_HTREF1
44.2/F_4
place them to CPU within 1.5"
R169
510/F_4
CPUTEST25H
CPUTEST25L
R168
510/F_4
36 CPU_VDD0_RUN_FB_H
36 CPU_VDD0_RUN_FB_L
36 CPU_VDD1_RUN_FB_H
36 CPU_VDD1_RUN_FB_L
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
T4
T24
T27
CPUTEST23
CPUTEST18
CPUTEST19
VDDIO_FB_H
VDDIO_FB_L
VDDIO_FB_H 37
VDDIO_FB_L 37
36
36
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
CPU_DBREQ#
CPU_TDO
G10
AA9
AC9
AD9
AF9
AD7
H10
G9
+1.5VSUS
R375
R310
R309
300/F_4
1K/F_4
*300/F_4
CPU_DBREQ#
CPUTEST27
R160
CPUTEST25H
E9
CPUTEST25L
E8
place them to CPU within 1.5"
CPUTEST21
AB8
CPUTEST20
AF7
T108
CPUTEST24
AE7
CPUTEST22
AE8
T5
CPUTEST12
AC8
T3
CPUTEST27
AF8
*0_4/S
C2
AA6
A3
A5
B3
B5
C1
CPUTEST29H
R116
T46
80.6/F_4
T50
FOX PZ63826-284R-41F
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2)
MLX 47296-4131
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2)
TYC 4-1903401-2
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2)
Route as 80ohm, diff
CN4
+1.5VSUS
B
CPU_LDT_RST_HTPA#
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDT Connector
Serial VID
+1.5VSUS
+1.5V
R203
R204
*0_4/S
*0_4/S
*0_4/S
1K/F_4
1K/F_4
+1.5VSUS
+1.5V
VFIX MODE
SVC
SVD
VID Override table (VDD)
Output Voltage
B
SI Change HDT connector fo FFC type
R181
*1K/F_4
CPU_SVC_R
CPU_SVD_R
CPU_PWRGD
R182
*1K/F_4
R188
R189
R191
CPU_SVC
CPU_SVD
CPU_PWRGD_SVID_REG
CPU_SVC 36
CPU_SVD 36
CPU_PWRGD_SVID_REG
0
0
1
1
36
0
1
0
1
CPUTEST12
CPUTEST19
CPUTEST18
CPUTEST20
CPUTEST21
CPUTEST22
CPUTEST24
R47
R104
R106
R311
R53
R52
R49
1.1V
1.0V
0.9V
0.8V
1K/F_4
1K/F_4
1K/F_4
1K/F_4
1K/F_4
1K/F_4
1K/F_4
R198
R197
R199
*220_4
*220_4
*220_4
HDT CONN
88511-2001-20p-l
Can remove on MP
A
+3V
+1.5VSUS
+1.5VSUS
C718
0.1U/10V_4
R224
R225
10K/F_4
300_4
+1.5VSUS
+1.5VSUS
R187
R373
10K/F_4
1K/F_4
2
5 CPU_THERMTRIP_L#
2
CPU_PROCHOT_L#
R209
R219
*0_4/S
*0_4/S
Q26
CPU_PROCHOT_R#
12
CPU_THERMTRIP_L#
1
Q23
MMBT3904
3
A
CPU_THERMTRIP# 13
U30
TC7SH08FU
CPU_LDT_RST_HTPA#
4
5
2
1
3
CPU_LDT_RST#
32 CPU_PROCHOT#
1
CPU_PROCHOT_R#
3
MMBT3904
PROJECT : R22
Quanta Computer Inc.
Size
Custom
NB5/RD2
Document Number
EC new option
S1G4 HT,CTL I/F 1/3
3
of
43
1
Rev
1A
Date: Wednesday, September 15, 2010Sheet
5
4
3
2
A
B
C
D
E
+1.5VSUS
+0.9V
U19B
+0.9V
VDDR = 0.9V for 25W & 35W CPU
VDDR = 1.05V for 35W & 45W CPU
7 MEM_MB_DATA[0..63]
DDR_VTTREF
R77
*0_4
CPU_VTT_SENSE 37
6,7,37
R306
*0_4/S
PLACE THEM CLOSE TO
CPU WITHIN 1"
Processor Memory Interface
U19C
MEM:DATA
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
D10
C10
B10
AD10
AF10
AE10
R312
R308
C547
10U/6.3V_8
6 MEM_MA_RESET#
6 MEM_MA0_ODT0
6 MEM_MA0_ODT1
39.2/F_4
M_ZP
39.2/F_4
M_ZN
VDDR1
MEM:CMD/CTRL/CLK
VDDR5
VDDR2
VDDR6
VDDR3
VDDR7
VDDR4
VDDR8
VDDR9
MEMZP
MEMZN
VDDR_SENSE
MA_RESET_L
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_RAS_L
MA_CAS_L
MA_W E_L
SOCKET_638_PIN
W 10
AC10
AB10
AA10
A10
Y10
CPU_VTT_SENSE
04
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_DATA[0..63]
6
4
Reserved
MEM_MA_RESET#
H16
MEMVREF
MB_RESET_L
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_RAS_L
MB_CAS_L
MB_W E_L
W 17
MEMVREF_CPU
B18
MEM_MB_RESET#
W 26
W 23
Y26
V26
W 25
U22
J25
H26
P22
R22
A17
A18
AF18
AF17
R26
R25
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W 24
J23
J24
R24
U26
J26
U25
U24
U23
MEM_MB_RESET# 7
MEM_MB0_ODT0 7
MEM_MB0_ODT1 7
T112
MEM_MB0_CS#0 7
MEM_MB0_CS#1 7
T15
MEM_MB_CKE0 7
MEM_MB_CKE1 7
MEM_MB_CLK5_P 7
MEM_MB_CLK5_N 7
T119
T120
T110
T109
MEM_MB_CLK4_P 7
MEM_MB_CLK4_N 7
MEM_MB_ADD[0..15]
7
C202
0.01U/16V_4
C195
1000P/50V_4
4
T14
T12
6 MEM_MA0_CS#0
6 MEM_MA0_CS#1
T13
T11
6 MEM_MA_CKE0
6 MEM_MA_CKE1
6 MEM_MA_CLK5_P
6 MEM_MA_CLK5_N
T34
T31
T8
T9
6 MEM_MA_CLK4_P
6 MEM_MA_CLK4_N
6 MEM_MA_ADD[0..15]
T19
V22
U21
V19
T20
U19
U20
V20
J22
J20
N19
N20
E16
F16
Y16
AA16
P19
P20
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
R20
R23
J21
R19
T22
T24
3
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
6 MEM_MA_BANK0
6 MEM_MA_BANK1
6 MEM_MA_BANK2
6 MEM_MA_RAS#
6 MEM_MA_CAS#
6 MEM_MA_WE#
MEM_MB_BANK0 7
MEM_MB_BANK1 7
MEM_MB_BANK2 7
MEM_MB_RAS# 7
MEM_MB_CAS# 7
MEM_MB_WE# 7
+0.9V
Place close to socket
C101
4.7U/6.3V_6
C416
4.7U/6.3V_6
C415
4.7U/6.3V_6
C98
0.22U/6.3V_4
C96
0.22U/6.3V_4
C405
0.22U/6.3V_4
C402
0.22U/6.3V_4
7 MEM_MB_DM[0..7]
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
A12
B16
A22
E25
AB26
AE22
AC16
AD12
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
2
C102
4.7U/6.3V_6
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
SOCKET_638_PIN
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W 22
W 21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W 16
W 14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W 11
AB14
AA14
AB12
AA12
E12
C15
E19
F24
AC24
Y19
AB16
Y13
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W 15
W 12
W 13
3
MEM_MA_DM[0..7]
6
2
+0.9V
C107
C104
1000P/50V_4 1000P/50V_4
C393
1000P/50V_4
C390
1000P/50V_4
C115
180P/50V_4
C114
180P/50V_4
C387
180P/50V_4
C100
180P/50V_4
+1.5VSUS
R184
+3VS5
R196
1K/F_4
U12
*.1U/10V_4
C417
0_4
Reserved for AMD suggest
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
MEM_MB_DQS0_P
MEM_MB_DQS0_N
MEM_MB_DQS1_P
MEM_MB_DQS1_N
MEM_MB_DQS2_P
MEM_MB_DQS2_N
MEM_MB_DQS3_P
MEM_MB_DQS3_N
MEM_MB_DQS4_P
MEM_MB_DQS4_N
MEM_MB_DQS5_P
MEM_MB_DQS5_N
MEM_MB_DQS6_P
MEM_MB_DQS6_N
MEM_MB_DQS7_P
MEM_MB_DQS7_N
MEM_MA_DQS0_P
MEM_MA_DQS0_N
MEM_MA_DQS1_P
MEM_MA_DQS1_N
MEM_MA_DQS2_P
MEM_MA_DQS2_N
MEM_MA_DQS3_P
MEM_MA_DQS3_N
MEM_MA_DQS4_P
MEM_MA_DQS4_N
MEM_MA_DQS5_P
MEM_MA_DQS5_N
MEM_MA_DQS6_P
MEM_MA_DQS6_N
MEM_MA_DQS7_P
MEM_MA_DQS7_N
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
3
1
+
-
1
*OPA343NA/3K
R185
1
*10_4
2
MEMVREF_CPU
1
4
R193
1K/F_4
C423
*0.47u/6.3V_4
2
R183
*10K/F_4
*0_4
*0_4
Size
Custom
NB5/RD2
R186
R180
PROJECT : R22
Quanta Computer Inc.
Document Number
S1G4 DDRII MEMORY I/F 2/3
4
of
43
E
Rev
1A
Date: Wednesday, September 15, 2010 Sheet
A
B
C
D
5
4
3
2
1
U19F
U19E
+VCORE
+VCORE
D
+CPUVDDNB
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
K16
M16
P16
T16
V16
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
4A
+1.5VSUS
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
SOCKET_638_PIN
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
+1.5VSUS
2A
C
+1.5VSUS
+1.5VSUS
R226
2K/F_4
R206
2K/F_4
R216
1K/F_4
R201
1K/F_4
R176
1K/F_4
32,40
MBCLK
Q27
MMBT3904
MBCLK
3
1
D20
CPU_SIC
CPU_SIC 3
1
RB501V-40
32,40
B
2
2
3
1
RB501V-40
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
MBDATA
MBDATA
Q25
MMBT3904
1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
SOCKET_638_PIN
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
+VCORE
05
BOTTOM SIDE DECOUPLING
C235
22U/6.3V_8
C249
22U/6.3V_8
C266
22U/6.3V_8
C275
0.22U/6.3V_4
C274
0.01U/16V_4
C273
180P/50V_4
D
C201
22U/6.3V_8
+VCORE
C261
22U/6.3V_8
C270
22U/6.3V_8
C247
22U/6.3V_8
C234
22U/6.3V_8
C198
0.22U/6.3V_4
C199
C197
0.01U/16V_4 180P/50V_4
+CPUVDDNB
+1.5VSUS
C243
22U/6.3V_8
C229
22U/6.3V_8
C256
22U/6.3V_8
C231
22U/6.3V_8
C246
22U/6.3V_8
C257
C276
0.22U/6.3V_4 0.22U/6.3V_4
C277
180P/50V_4
C
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.5VSUS
C128
4.7U/6.3V_6
+1.5VSUS
C137
4.7U/6.3V_6
C309
4.7U/6.3V_6
C307
4.7U/6.3V_6
C130
0.22U/6.3V_4
C134
0.22U/6.3V_4
2
C144
C141
C208
C193
0.22U/6.3V_4 0.22U/6.3V_4 0.01U/16V_4 0.1U/10V_4
C305
180P/50V_4
C303
180P/50V_4
C209
0.1U/10V_4
CPU_SID
CPU_SID 3
B
2
D19
CPU_ALERT
CPU_ALERT 3
PROCESSOR POWER AND GROUND
+1.5V_VGA
+1.8V_VGA
+VGA_CORE
EC10
EC14
EC8
*0.01U/16V_4
*0.01U/16V_4
*0.01U/16V_4
+3V
+3V
*0.1U/10V_4
*0.1U/10V_4
+VGA_CORE
EC5
+3V
EC12
+3V
+3V
R356
200/F_6
R367
10K/F_4
R368
10K/F_4
R360
+3V
10K/F_4
U22
C619
0.1U/10V_4
32
32
MBCLK2
MBDATA2
8
7
6
SCLK
SDA
ALERT#
OVERT#
VCC
DXP
DXN
GND
1
2
3
5
+1.5V_VGA
H_THRMDA 3
C621
1000P/50V_4
H_THRMDC
3
Q24
R190
*0_4/S
D18
3920_RST#
3920_RST# 32
+5V
EC6
*0.01U/16V_4
EC13
*0.01U/16V_4
+1.5VSUS
+1.8V_VGA
EC11
EC9
*0.01U/16V_4
*0.01U/16V_4
+3V
+1.1V
+3V
3
MMBT3904
2
2
1
CH501H-40PT
ECPWROK
13 PM_THERM#
A
4
ECPWROK 16,20,32
+VGA_CORE
MSOP
G786P8
R374
10K/F_4
PQ30
Q36
MMBT3904
3
*2N7002E-G
SMBALERT#
SMBALERT#
For fix HyperTransport nets
across plane splits
+3V
1
A
R194
10K/F_4
+1.5V
3
R200
10K/F_4
TEMP_FAIL 18
2
2
PROJECT : R22
Quanta Computer Inc.
Size
Custom
NB5/RD2
Document Number
3 CPU_THERMTRIP_L#
CPU_THERMTRIP_L#
1
ADD VGA TEMP_ FAIL function
M92 is active Hi
1
S1G4 PWR & GND 3/3
5
of
43
1
Rev
1A
Date: Wednesday, September 15, 2010 Sheet
5
4
3
2

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