PR31700user_guide_2.pdf

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INTEGRATED CIRCUITS
MIPS
PR31700
32-bit RISC
microprocessor
MIPS PR31700
32-bit RISC microprocessor
User Manual
Version 0.3
Preliminary specification
1998 Sep 30
Philips
Semiconductors
Philips Semiconductors
Preliminary
Contents
PR31700 V0.3
Chapter 1 Overview...........................................................................................................
Overview ..........................................................................................................................
References ........................................................................................................................
Chapter 2 Pin Descriptions ..............................................................................................
Overview ..........................................................................................................................
Pins ...................................................................................................................................
Memory Pins ....................................................................................................................
Bus Arbitration Pins .........................................................................................................
Clock Pins ........................................................................................................................
CHI Pins ...........................................................................................................................
IO Pins ..............................................................................................................................
Reset Pins ..........................................................................................................................
Power Supply Pins ...........................................................................................................
SIB Pins ............................................................................................................................
SPI Pins ............................................................................................................................
UART and IR Pins ...........................................................................................................
Video Pins ........................................................................................................................
Endianess Pin ...................................................................................................................
Test Pins ............................................................................................................................
Spare Pins .........................................................................................................................
Power Supply Pins ............................................................................................................
Pin Usage Information .....................................................................................................
Chapter 3 CPU Module......................................................................................................
Overview ..........................................................................................................................
Related Pins ......................................................................................................................
CPU Core .........................................................................................................................
Description .......................................................................................................................
CPU Interface ...................................................................................................................
Block Diagram .................................................................................................................
Write Buffer .....................................................................................................................
Interface Controller ..........................................................................................................
DMA Arbitration ..............................................................................................................
CPU Stop Mode ...............................................................................................................
Test Modes .......................................................................................................................
Test Bypass Mode ............................................................................................................
CPU Test Mode ................................................................................................................
Chapter 4 BIU Module .......................................................................................................
Overview ..........................................................................................................................
Block Diagram .................................................................................................................
Address Decoder ..............................................................................................................
System Address Map ........................................................................................................
Address Generation ..........................................................................................................
Address Re-Mapper Logic ...............................................................................................
Chip Select Controller ......................................................................................................
Description .......................................................................................................................
Access Mapping ...............................................................................................................
CS3-CS0 and MCS3-MCS0 Timing ................................................................................
Card 2 and Card 1 ............................................................................................................
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Philips Semiconductors
Preliminary
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PR31700 V0.3
CS0 Size Configuration ....................................................................................................
Show PR31700 .................................................................................................................
DRAM and SDRAM Controller ......................................................................................
Memory Chips Supported ................................................................................................
DRAM and SDRAM Configurations ...............................................................................
DRAM ..............................................................................................................................
DRAM Initialization ........................................................................................................
SDRAM ............................................................................................................................
SDRAM Initialization ......................................................................................................
SDRAM Mode Register ...................................................................................................
SDRAM Power Down Mode ...........................................................................................
SDRAM Timing ...............................................................................................................
Arbitration ........................................................................................................................
Refresh Controller ............................................................................................................
External Bus Master .........................................................................................................
Watch Dog Timer .............................................................................................................
Memory Power Down ......................................................................................................
Memory Connections .......................................................................................................
BIU Registers ...................................................................................................................
Memory Configuration 0 Register ...................................................................................
Memory Configuration 1 Register ...................................................................................
Memory Configuration 2 Register ...................................................................................
Memory Configuration 3 Register ...................................................................................
Memory Configuration 4 Register ...................................................................................
Memory Configuration 5 Register ...................................................................................
Memory Configuration 6 Register ...................................................................................
Memory Configuration 7 Register ...................................................................................
Memory Configuration 8 Register ...................................................................................
Chapter 5 SIU Module .......................................................................................................
Overview ..........................................................................................................................
Implementation ................................................................................................................
Block Diagram .................................................................................................................
DMA Controller Description ...........................................................................................
Address Decoder Description ..........................................................................................
Internal PR31700 Registers ..............................................................................................
SIU Registers ...................................................................................................................
SIU Test Register .............................................................................................................
Chapter 6 Clock Module ...................................................................................................
Overview ..........................................................................................................................
Related Pins ......................................................................................................................
Implementation ................................................................................................................
Block Diagram .................................................................................................................
Clock Module Description ...............................................................................................
Clock Registers ................................................................................................................
Clock Control Register .....................................................................................................
Chapter 7 CHI Module .......................................................................................................
Overview ..........................................................................................................................
Related Pins ......................................................................................................................
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Philips Semiconductors
Preliminary
Contents
PR31700 V0.3
Interface Requirements .................................................................................................... 84
Frame Structure and Serial Timing .................................................................................. 84
Configurations .................................................................................................................. 89
Implementation ................................................................................................................ 91
Block Diagram ................................................................................................................. 91
Transmitter ....................................................................................................................... 92
Receiver ............................................................................................................................ 92
Clock and Control Generation ......................................................................................... 92
DMA Address Generation ................................................................................................ 95
Related Interrupts ............................................................................................................. 97
CHI Registers ................................................................................................................... 98
CHI Control Register ....................................................................................................... 98
CHI Pointer Enable Register ............................................................................................ 100
CHI Receive Pointer A Register ...................................................................................... 101
CHI Receive Pointer B Register ...................................................................................... 102
CHI Transmit Pointer A Register ..................................................................................... 102
CHI Transmit Pointer B Register ..................................................................................... 103
CHI Size Register ............................................................................................................. 103
CHI RX Start Register ..................................................................................................... 104
CHI TX Start Register ...................................................................................................... 104
CHI TX Holding Register ................................................................................................ 104
CHI RX Holding Register ................................................................................................ 104
Chapter 8 Interrupt Module .............................................................................................. 107
Overview .......................................................................................................................... 107
Implementation ................................................................................................................ 108
Block Diagram ................................................................................................................. 108
Interrupt Logic Description .............................................................................................. 109
Interrupt Registers ............................................................................................................ 110
Interrupt Status 2 Register ................................................................................................ 112
Interrupt Status 3 Register ................................................................................................ 113
Interrupt Status 4 Register ................................................................................................ 114
Interrupt Status 5 Register ................................................................................................ 114
Interrupt Status 6 Register ................................................................................................ 116
Clear Interrupt 1 Register ................................................................................................. 116
Clear Interrupt 2 Register ................................................................................................. 116
Clear Interrupt 3 Register ................................................................................................. 116
Clear Interrupt 4 Register ................................................................................................. 116
Clear Interrupt 5 Register ................................................................................................. 117
Enable Interrupt 1 Register .............................................................................................. 117
Enable Interrupt 2 Register .............................................................................................. 117
Enable Interrupt 3 Register .............................................................................................. 117
Enable Interrupt 4 Register .............................................................................................. 117
Enable Interrupt 5 Register .............................................................................................. 117
Enable Interrupt 6 Register .............................................................................................. 117
Chapter 9 I/O Module ........................................................................................................ 119
Overview .......................................................................................................................... 119
Related Pins ...................................................................................................................... 119
Implementation ................................................................................................................ 120
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