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19-1244; Rev 0; 6/97
MAX1160 Evaluation Kit
_______________General Description
The MAX1160 evaluation kit (EV kit) evaluates the per-
formance of the MAX1160/MAX1161 monolithic, high-
speed 10-bit analog-to-digital converters (ADCs). The
ADCs must be ordered separately.
The MAX1160 and MAX1161 have a ±2V analog input
range and can digitize an analog input signal into 10-bit
words at minimum update rates of 20Msps and
40Msps, respectively. The devices are pin compatible,
and all input/output logic is TTL compatible.
____________________________Features
o
20Msps/40Msps Conversion Rate
o
On-Board Clock Drivers
o
Data Output and Strobe Signal
o
User-Selectable Capture Clock
o
On-Board Reference Drivers
Evaluates: MAX1160/MAX1161
________________EV Kit Applications
Evaluation of MAX1160/MAX1161
Engineering System Prototype Aid
Incoming Inspection Tool
Guide for System Layout
______________Ordering Information
PART
MAX1160EVKIT*
TEMP. RANGE
0°C to +70°C
*
Evaluates either MAX1160_CPI or MAX1161_CPI, which must
be ordered separately.
CLK
+
TTL
-
DGND
+5
COMP
CCLK
MAX1160
EVALUATION KIT
-5.2
VFT
CLK
DGND
DAUGHTER BOARD
+2.5V
REF
LATCHES
-1
MAX1160
MAX1161
VFB
Dout
10
10
12-BIT DAC
(80 MSPS MAX)
VIN
VIN
10
DAC
OUT
AGND
-A5.2V
+A5
- D5.2V
+D5V
ADC OUT (TTL)
THE MAX1160 EV KIT CONSISTS OF FIVE SEPARATE SECTIONS:
1) REFERENCE CIRCUITS
2) CLOCK CIRCUITS
3) MAX1160 OR MAX1161 10-BIT ADC (NOT INCLUDED WITH THE BOARD)
4) OUTPUT LATCHES AVAILABLE THROUGH 26-PIN FEMALE RIBBON CONNECTOR
5) THE DAC RECONSTRUCTION BOARD IS A SEPARATE DAUGHTERBOARD (2.5" x 3") THAT DIRECTLY INTERFACES WITH THE MAX1160 EV KIT MAIN BOARD (4" x 7.5").
Figure 1. Functional Diagram
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
MAX1160 Evaluation Kit
Evaluates: MAX1160/MAX1161
___________________________________________MAX1160 EV Kit Component List
DESIGNATION QTY
C1–C7, C10
C20,
C22–C28,
C30, C31, C32
C21, C29
C50–C58
D1
FB1, FB2, FB3
P1
P1/Receptacle
P2, P3
PJ1, PJ2
R1, R2
R3
R10, R11, R12
R20, R21
R26, R27, R30
8
11
2
9
1
3
1
1
2
2
2
1
3
2
3
DESCRIPTION
10µF, 25V, 0.10" tantalum capacitors
0.01µF chip capacitors
0.1µF chip capacitors
0.01µF, 10% ceramic capacitors
Lead-mounted hot-carrier diode
Lead-mounted ferrite beads
9-pin power connector
Molex/09-18-5094
9-pin power-connector, receptacle
Molex/03-09-1093
Ribbon-plug connectors
Probe connectors
10kΩ, 12-turns potentiometers
2kΩ, 12-turns potentiometer
51Ω, 5%, 1/8W resistors
820Ω, 5%, 1/8W resistors
20kΩ, 5%, 1/8W resistors
DESIGNATION QTY
R28
R32
R33
RN1, RN2
TP1, TP2, TP3,
AG, DG, STEP
U1
U2
U3
U5
U7, U8
None
None
None
None
None
None
None
1
1
1
2
6
1
1
1
1
2
3
8
1
4
4
1
1
DESCRIPTION
1MΩ, 5%, 1/8W resistor
5.1kΩ, 5%, 1/8W resistor
10kΩ, 5%, 1/8W resistor
10kΩ, 708A-type 8-pin SIP resistors
76 mil-diameter hole,
test-point terminal
Device under test, 10-bit ADC
+2.5V precision voltage reference
Op amp, low noise
Single, fast TTL comparator, 8 DIP
HEX D flip-flop, TTL, fast series
BNC connector
Crimp female terminal for P3
Crimp male terminal for P3
Nylon screw, 4-40, 3/16", round head
Nylon standoff, 1", round
SIP socket strip, 20SIP break-away
28-pin DIP socket, 0.6" (U1)
____________________________________________Daughterboard Component List
DESIGNATION QTY
C1, C2
C10–C16
C21–C25
D1
DB792 PCB
FB1, FB2
P2, P3
R1
R2
R3
R4
R5
2
7
5
1
1
2
2
1
1
1
1
1
DESCRIPTION
10µF, 25V, 0.10" tantalum capacitors
0.1µF chip capacitors
0.1µF, 10% ceramic capacitors
1.2V reference, 2-terminal IC
Printed circuit board
Lead-mounted ferrite beads
26-pin, dual-row, vertical PCB-mount
connectors
10kΩ, 12-turns potentiometer
7.5kΩ, 5%, 1/8W resistor
22Ω, 5%, 1/8W resistor
10kΩ, 5%, 1/8W resistor
15kΩ, 5%, 1/8W resistor
DESIGNATION QTY
R6
R7, R8
R11, R12
R20, R21
R22
TP1, AG, DG
U9
U10
U11
None
None
1
2
2
2
1
3
1
1
1
1
1
DESCRIPTION
20kΩ, 5%, 1/8W resistor
1kΩ, 5%, 1/8W resistors
150Ω, 5%, 1/8W resistors
820Ω, 5%, 1/8W resistors
200Ω, 5%, 1/8W resistor
76-mil-diameter hole,
test-point terminals
100MHz, 12-bit TTL DAC
Low-noise op amp
Low-distortion op amp
BNC connector
Crimp male terminal for P3
2
_______________________________________________________________________________________
MAX1160 Evaluation Kit
_______________Detailed Description
Power Supplies
The MAX1160 evaluation kit (EV kit) requires four
power-supply sources: analog -5.2V (-A5.2V), analog
+5V (+A5V), and digital -5.2V (-D5.2V), and digital +5V
(+D5V). P1 is the power connector. (See Figure 2.)
Table 1 shows the recommended operating voltage
range.
AGND and DGND are isolated on the MAX1160/
MAX1161. Both -A5.2V and +A5V are the analog sup-
ply sources. As with most very-high-speed analog-to-
digital converters (ADCs), grounding is critical.
Therefore, the ground-plane technique is the one most
desirable for the MAX1160/MAX1161. To use this
method, split the AGND and DGND planes and tie
them together at the device through an RF bead. The
MAX1160 EV Kit has four layers: top signal, ground
(AGND and DGND) planes, power plane, and bottom
signal. The two ground planes are connected at the
device through a ferrite bead (RF3). All three ferrite
beads (RF1, RF2, RF3) are located close to the ADC.
Evaluates: MAX1160/MAX1161
Power-Supply Hookups
Power Supplies and Grounding
The MAX1160/MAX1161 require two analog supply
voltages: -A5.2V and +A5V. The +A5V supply is com-
mon to analog V
CC
(pins 18 and 25) and digital DV
CC
(pins 14 and 28). A ferrite bead in series with each sup-
ply (RF1 and RF2) reduces the transient noise injected
into V
CC
. The bead (RF1 or RF2) to MAX1160/MAX1161
connections should not be shared with any other
device. Bypass each power-supply pin as closely as
possible to the device (0.1µF to AGND for each V
EE
and V
CC
pin and 0.01µF to DGND for the DV
CC
pin).
Total power dissipation is typically 1.9W, including the
MAX1160/MAX1161 (1.1W typ).
Reference Circuit
The MAX1160/MAX1161 requires the use of two voltage
references: VFT and VFB. VFT (+2.5V typ) is the force
for the top of the voltage-reference ladder, and VFB
(-2.5V typ) is the force for the bottom. Both voltages are
applied across an internal 900Ω reference ladder. In
addition, there are three reference-ladder taps: VST,
Table 1. Recommended Power-Supply
Operating Range
POWER
SUPPLY
(V)
-A5.2
+A5
-D5.2
+D5
MIN
(V)
-4.95
+4.75
-4.95
+4.75
TYP
(V)
-5.20
+5.00
-5.20
+5.00
MAX
(V)
-5.45
+5.25
-5.45
+5.25
TYP
CURRENT
(mA)
60
240
15
60
9
6
3
8
5
2
FEMALE
TERMINAL
7
4
1
P1
(TOP VIEW)
Figure 2. P1 Power-Supply Connector’s Pin Assignment
Table 2. Pin Assignments
PIN
1
2
3
4
5
6
7
8
9
DESCRIPTION
Analog -5.2V
Analog -5.2V Return #1 (AGND)
Analog -5.2V Return #2 (AGND)
Analog +5V
Analog +5V Return (AGND)
Digital -5.2V Return (DGND)
Digital +5V
Digital +5V Return (DGND)
Digital -5.2V
-5.2 V
+5V
- 5.2 V
+5V
+
-
+
-
+
-
+
-
2
3
1
4
5
6
9
7
8
P1 POWER CONNECTOR
Figure 3. P1 Connector/Hookup
3
_______________________________________________________________________________________
MAX1160 Evaluation Kit
Evaluates: MAX1160/MAX1161
VRM, and VSB. VST is the top of the reference-ladder
tap (+2V); VRM is the middle point (0.0V typ); and VSB is
(-2V). The voltages at VST and VSB are the full-scale
input voltages expected of the device when VFT and
VFB are driven to the recommended voltages (+2.5V
and -2.5V, respectively). Use VST and VSB to monitor
the actual full-scale input voltages (±2V) by adjusting
VFT and VFB (Table 3). These adjustments interact with
one another; repeat them as needed until VST and VSB
settle at the desired voltages. Do not drive VRM as is
commonly done with a standard flash ADC converter.
When not being used, decouple VST, VRM, and VSB
with a 0.01µF, surface-mount chip capacitor from each
tap to AGND, to minimize high-frequency noise injection.
As shown in Figure 17, U2 is the +2.5V reference with
±150mV of adjustable range (R1 potentiometer). U3 is
an inverting amplifier. Its tolerance is 5% with ±300mV
of adjustable range (R2 potentiometer). Maxim recom-
mends that VFT and VFB be operated to within ±2%
(or ±2.5V ±50mV) to maintain accuracy within the
specified limit. Before each MAX1160 EV kit board is
shipped, VFT and VFB are adjusted to ±2.5V (±5mV),
respectively. For each new MAX1160/MAX1161, read-
just VST and VSB. All measurements must be refer-
enced to the AGND test point. (See Table 3.)
Figure 4a shows one type of reference driver. Figure 4b
shows another way to drive the reference circuits using
force and sense. The alternate circuit provides better
control of plus full-scale (+FS) and minus full-scale
(-FS) errors by sensing VST and VSB to ±2.0V, respec-
tively. VST and VSB are high-impedance nodes, requir-
ing additional precaution when routing (PCB layout).
MAX1160/MAX1161 ADCs
The MAX1160 is a 10-bit ADC capable of digitizing an
input signal with a 20Msps minimum update rate. The
MAX1161 is pin compatible with the MAX1160, except it is
faster: the sampling frequency is 40Msps. On both
devices, the expected full-scale analog input range is from
VST to VSB. The analog input is latched at CLK’s leading
edge. There are 11 digital TTL outputs. D0–D9 are the
parallel TTL output bits, with D0 the least significant bit
(LSB), D9 the most significant bit (MSB), and D10 the
overrange bit. The data outputs are latched at CLK’s rising
edge, with a 14ns propagation delay. There is one clock
latency between CLK and valid output data (Figure 5). The
output code is straight binary.
Table 3. Reference Adjustment
VST
Test Point
Min
Typ
Max
Adjust
U1, pin 20
1.95V
2.00V
2.05V
R1
VSB
-2.05V
-2.00V
-1.95V
R2
U1, pin 23
U2
+2.5VREF
VFT
R
R
-
U3
-2.5 V
VFB
NOTE: The MAX1160/MAX1161 (especially reference taps
VFT, VFB, VST, and VRM) are sensitive to electrostatic dis-
charge (ESD).
Figure 4a. Reference Driver
Table 4. Output Coding
ANALOG
INPUT
<-2.0V
-2.0V + 1LSB
0V
+2.0V - 1LSB
>2.0V + 1/2LSB
D12
(OVERRANGE
BIT)
0
0
0
0
1
DATA
OUTPUT
CODE
00 0000 0000
00 0000 000Ø
ØØ ØØØØ ØØØØ
11 1111 111Ø
11 1111 1111
+
-
OUT
+2.5V
REF
+2.5 V
+2.0 V
10 k
0.1
10 k
10 k
NOTE: Ø indicates the flickering bit between logic 0 and 1.
4
Figure 4b. Alternative Reference Driver
_______________________________________________________________________________________
+
+
-
≈
+2.5 V
+2.0 V
-2.0 V
≈
-2.5 V
VFT
VST
VSB
VFB
MAX1160 Evaluation Kit
Pin 21 is the analog input pin. Selecting the analog
input driver for the MAX1160/MAX1161 is simpler than
with most flash ADCs because the input impedance
and input capacitance are typically 300kΩ and 5pF,
respectively. For example, at 10MHz and 4Vp-p sine-
wave input, the input driver source requires only
0.648mA of peak output current (4πFC).
The analog input is fed directly from a BNC (VIN). R10
(51Ω) is the analog input source termination mounted
on a socket as a user-selectable termination. The ana-
log input pin has no circuit protection. Its maximum rat-
ing is from VFT to VFB (±2.5V). Use a voltage limiter to
protect the input pin from permanent damage in appli-
cations with an analog input range greater than ±2.5V.
(See the
Input and Latchup Protection
section.)
rate, and low jitter) is more difficult than finding a sine-
wave, low-jitter generator. U5 (MAX9686, TTL-voltage
comparator) provides most of the above requirements for
driving the ADC (except the low-jitter generator). The CLK
signal should be a sine-wave signal with an amplitude not
to exceed ±3V (input common-mode limitation of U5). R11
(51Ω) is the CLK source termination. Use R3 to adjust the
CLK IN duty cycle. CLK IN is in phase with CLK and has a
6ns typical propagation delay. Due to the internal
track/hold amplifier (THA), keep the positive clock (CLK
IN) pulse width from 10ns to 300ns for the MAX1161 and
from 20ns to 300ns for the MAX1160. When operating the
ADC faster than 3Msps, keep the clock duty cycle at
approximately 50% ±10%. Probe jack PJ1 is the monitor-
ing test point for CLK IN. Use this test point when adjust-
ing the clock duty cycle.
A falling edge at CLK IN (pin 17) causes the internal
THA to go into track mode. Keep the MAX1160/
MAX1161 in track mode at start-up or when the device
is idle for an extended period of time. This setup pre-
vents the internal THA from going into saturation due to
droop. The EV kit provides a logic low to the ADC clock
when the pulse generator (CLK) is removed from the
evaluation board.
Evaluates: MAX1160/MAX1161
Input Clock Driver
CLK is the single-ended input clock to the MAX1160 EV
kit; CLK IN is the input clock to the ADC; and CCLK
is the capture clock used for the output latches (U7
and U8).
The MAX1160/MAX1161’s clock input requires a TTL-logic
level of 6ns or faster to reduce the noise. Fast TTL-family
components (74FXX) fit well in this application. Finding a
square-wave generator (TTL logic up to 40MHz, fast slew
N
N+1
CLK IN
2.4V
6nS
typ.
3.5V
Rise Time
≤
6nSEC
DATA OUT
(Actual)
2.4V
Invalid
Data
Invalid
Data
(N-2)
0.8V
0.5V
(N-1)
t
pd1
(N)
(14 nS typ.)
DATA OUT
(Equivalent)
(N-2)
INVALID
DATA
(N-1)
INVALID
DATA
(N)
Figure 5. Digital Output Characteristic of the MAX1160/MAX1161
_______________________________________________________________________________________
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