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DALLAS SEMICONDUCTOR
DS3131 Preliminary Data Sheet (V2)
January 26, 1999
DALLAS SEMICONDUCTOR
DS3131
BoSS
Bit SynchronouS
HDLC CONTROLLER
40 Port / 40 Channel HDLC Controller
with Option for Local Bus Access
Preliminary Data Sheet
Version 2
January 26, 1999
1
DALLAS SEMICONDUCTOR
DS3131 Preliminary Data Sheet (V2)
January 26, 1999
REVISION HISTORY
Version 1 (8/6/98)
Original release.
Version 2 (1/26/99)
1. The octet synchronous functionality was removed.
2. The throughput rate was changed from 164Mbps to 132Mbps.
3. The maximum PCI Bus speed was changed from 50MHz to 33MHz.
4. The polarity of the LBPXS input signal was changed and a pullup was added.
5. Added bit numbers to register descriptions.
6. The RCSO & TCSO outputs were removed.
7. Layer One port modes 2, 3, & 4 were removed.
8. The Master Control (MC) register was modified to allow the BERT Port Select Bits.
9. The transmit & receive DMA throttle bits were merged (see the MC register).
10. The COFA status bits were removed.
11. Changed BERT ones and zeros detector from 32 consecutive to 31 consecutive.
12. Changed BERT Bit and Error Counters to count during loss of receive synchronization.
13. Changed the HDLC channel priority scheme from high/low select to a quantized selection.
14. Added information about the DMA queues full & empty states.
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DALLAS SEMICONDUCTOR
DS3131 Preliminary Data Sheet (V2)
January 26, 1999
TABLE OF CONTENTS
Section 1: Introduction…………………………………………………………………………………….. 5
Section 2: Signal Description……………………………………………………………………………… 12
2.1 Overview / Signal Lead List………………………………………………………………… 12
2.2 Serial Port Interface Signal Description…………………………………………………… 22
2.3 Local Bus Signal Description………………………………………………………………. 23
2.4 JTAG Signal Description…………………………………………………………………… 26
2.5 PCI Bus Signal Description………………………………………………………………… 27
2.6 Supply & Test Signal Description…………………...…………………………………….. 30
Section 3: Memory Map……………………………………………………………………………………
3.0 Introduction…………………………………………………………………………………..
3.1 General Configuration Registers…………………………………………………………..
3.2 Receive Port Registers……………………………………………………………………..
3.3 Transmit Port Registers…………………………………………………………………….
3.4 HDLC Registers…………………………………………………………………………….
3.5 BERT Registers……………………………………………………………………………..
3.6 Receive DMA Registers…………………………………………………………………….
3.7 Transmit DMA Registers……………………………………………………………………
3.8 FIFO Registers………………………………………………………………………………
3.9 PCI Configuration Registers for Function 0…………..………………………………….
3.10 PCI Configuration Registers for Function 1…………………………………………….
Section 4: General Device Configuration & Status/Interrupt…………………………………………..
4.1 Master Reset & ID Register Description………………………………………………….
4.2 Master Configuration Register Description……………………………………………….
4.3 Status & Interrupt……………………………………………………………………………
4.3.1 Status & Interrupt General Description………………………………………
4.3.2 Status & Interrupt Register Description………………………………………
4.4 Test Register Description…………………………………………………………………..
Section 5: Layer One………………………………………………………………………………………
5.1 General Description…………………………………………………………………………
5.2 Port Register Description…………………………………………………………………..
5.3 BERT…………………………………………………………………………………………
5.4 BERT Register Description………………………………………………………………..
31
31
31
32
33
34
34
34
35
35
36
36
37
37
37
40
40
42
47
48
48
50
52
53
Section 6: HDLC………………………………………………………………………………………….. 58
6.1 General Description……………………………………………………………………….. 58
6.2 HDLC Register Description……...........................……………………..………………. 60
Section 7: FIFO……………………………………………………………………………………………
7.1 General Description & Example………………………………………………………….
7.2 FIFO Register Description………………………………………………………………..
66
66
68
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DALLAS SEMICONDUCTOR
DS3131 Preliminary Data Sheet (V2)
January 26, 1999
Section 8: DMA……………………………………………………………………………………………
8.0 Introduction…………………………………………………………………………………
8.1 Receive Side……………………………………………………………………………….
8.1.1 Overview……………………………………………………………………….
8.1.2 Packet Descriptors…………………………………………………………….
8.1.3 Free Queue…………………………………………………………………….
8.1.4 Done Queue……………………………………………………………………
8.1.5 DMA Configuration RAM……………………………………………………..
8.2 Transmit Side……………………………………………………………………………….
8.2.1 Overview………………………………………………………………………..
8.2.2 Packet Descriptors…………………………………………………………….
8.2.3 Pending Queue…………………………………………………………………
8.2.4 Done Queue…………………………………………………………………….
8.2.5 DMA Configuration RAM………………………………………………………
75
75
77
77
82
84
89
94
97
97
105
107
110
116
Section 9: PCI Bus………………………………………………………………………………………… 120
9.1 PCI General Description…………………………………………………………………… 120
9.2 PCI Configuration Register Description………………………………………………….. 126
Section 10: Local Bus……………………………………………………………………………………..
10.1 Local Bus General Description…………………………………………………………..
10.2 Local Bus Bridge Mode Control Register Description…………………………………
10.3 Examples of Bus Timing for Local Bus PCI Bridge Mode Operation………………..
Section 11: JTAG…………………………………………………………………………………………..
11.1 JTAG Operation……………………………………………………………………………
11.2 TAP Controller State Machine Description……………………………………………..
11.3 Instruction Register and Instructions……………………………………………………
11.4 Test Registers……………………………………………………………………………..
137
137
143
145
153
153
153
156
157
Section 12: AC Characteristics………………………………………………………………………….. 158
Section 13: Mechanical Dimensions……………………………………………………………………. 165
Section 14: Applications…………………………………………………………………………...……..
14.1 T1/E1 and T3/E3 Applications................................................................................
14.2 xDSL & Cable Modem Application..........................................................................
14.3 SONET/SDH Application........................................................................................
166
166
169
170
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DALLAS SEMICONDUCTOR
DS3131 Preliminary Data Sheet (V2)
January 26, 1999
SECTION 1: INTRODUCTION
The DS3131 BoSS HDLC Controller is based on Dallas Semiconductor’s DS3134 CHATEAU HDLC
Controller. BoSS & CHATEAU share the same DMA & FIFO structure and the signal locations for the
Local Bus and the PCI Bus are the same. The primary difference between the two devices is in the Layer
One functionality. CHATEAU supports channelized T1/E1 whereas BoSS does not. Hence the Layer One
functions in CHATEAU that support channelized interfaces does not exist in BoSS.
The DS3131 BoSS consists of 40 Bit Synchronous HDLC controllers. The primary features of the device
are listed in Table 1A. This data sheet is split in Sections along the major the blocks of the device as
shown in Figure 1A. Throughout the data sheet, certain terms will be used and these terms are defined in
Table 1B. The DS3131 device is designed to meet certain specifications and a listing of these governing
specifications is shown in Table 1C. The DS3131 can be operated in two configurations depending on
whether the Local Bus is enabled or not. See Figure 1B.
DS3131 Block Diagram
Figure 1A
Receive Direction
Transmit Direction
RC0
RD0
TC0
TD0
RC1
RD1
TC1
TD1
RC2
RD2
TC2
TD2
40 Bit
Sync.
HDLC
Controllers
(Sec. 6)
PCLK
PRST*
PAD[31:0]
PCBE[3:0]*
PPAR
PFRAME*
PIRDY*
PTRDY*
PSTOP*
PIDSEL
PDEVSEL*
PREQ*
PGNT*
PPERR*
PSERR*
PXAS*
PXDS*
PXBLAST*
RC39
RD39
TC39
TD39
Internal Control Bus
Local
Bus
Block
(Sec. 10)
(Sec. 5)
JTRST*
JTDI
JTMS
JTCLK
JTDO
JTAG
Test
Access
(Sec. 11)
LA[19:0]
LD[15:0]
LWR*(LR/W*)
LRD*(LDS*)
LIM
LINT*
LRDY*
LMS
LCS*
LHOLD(LBR*)
LHLDA(LBG*)
LBGACK*
LCLK
LBHE*
LBPXS
Pin Names in ( )
are active when
the device is in
the MOT mode
(i.e. LIM = 1)
Layer
One
Block
(Sec. 5)
FIFO
Block
(Sec. 7)
DMA
Block
(Sec. 8)
PCI
Block
(Sec. 9)
BERT
bblockdia
5

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