Intel 845E Client Schematics.PDF

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Intel (R) 845E Interactive
Client Reference Design
D
Revision X2
Last Change : 2002-09-26
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#
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Schematic Page
COVER SHEET
BLOCK DIAGRAM
BLOCK-POWER
MECH-ROUTE
NOTES
CPU-P4 BUS
CPU-P4 POWER
CPU-ITP
MCH-SYSBUS & CLOCK
MCH-AGP & DDR
MCH-POWER
CLK-ICS950201
DDR-DIMM 0
DDR-DIMM 1
ICH4-SYSBUS & PCI
ICH4-LPC & IDE & USB
ICH4-POWER
GLUE LOGIC
SIO0-LPC47M107
SIO1-LPC47N227
CONN-COM1/COM2/LPT
CONN-COM3/COM4/KBC
AC97-AD1885
LAN-10/100/1000 BUS
LAN-10/100/1000 CONN
VGA-COUGAR-01
VGA-COUGAR-02
VGA-COUGAR-03
CONN-PCI
CONN-01 IDE-FLOPPY
USB0-USB1-LAN0
USB2-USB5
SYSTEM CONTROL
DDR-POWER
POWER
Prefix
A_
AC_
APIC_
AUD_
CK_
EEn_
EN_
F_
FWH_
G_
GND_
GND
H_
I2C_
IDE_
INT_
KB_
L_
LANn_
LP_
M_
MIDI_
MS_
P_
SPn_
USB_
V_
ZV_
Netobject
CRITICAL ANALOG TRACES
AC97 SIGNAL
APIC SIGNAL
ANALOG AUDIO SIGNAL
CLOCK SIGNAL
SERIAL EEPROM LANn
ENABLE FOR POWER SOURCES
FLOPPY DISK SIGNAL
FIRMWARE HUB SIGNAL
AGP BUS SIGNAL
GND SIGNAL DERIVED
GND POWER
P4 HOSTBUS SIGNAL
I2C BUS SIGNAL
IDE SIGNAL
INTERRUPT SIGNAL
KEYBOARD SIGNAL
LPC BUS SIGNAL
LAN CONTROLLER n SIGNAL
LPT1284 SIGNAL
MEMORY BUS SIGNAL
MIDI SIGNAL
MOUSE SIGNAL
PCI BUS SIGNAL
SERIAL PORT n SIGNAL
USB PORT SIGNAL
POWER
ZV VIDEO PORT SIGNAL
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Changes from X1 to X2
All BAT54A (0-0031-1261) changed to BAT54 (0-0031-1104) due to wrong polarity
R712 changed from 10k to 15k to adjust voltage
PU R756 and R757 added @ U38.15 (PG_VDDR) and U38.16 (PG_V1V5)
Net on pins U3.54 and U3.55 separated (BSEL[0..1]) due to naming error
PU R758 added at CN34.7 (SYS_RESET#)
PU R759 added at U39.4 (VIDPWRGD)
C717 changed from 4u7 to 1u
R607 not populated
R571 and R572 not populated (FWH Test Pins)
R585 and R586 not populated (for LVDS 18 Bit)
R760 and C741 added to U7.50 to generate a V_3V3SB input delay for resume reset
R501 and R494 not populated due to PCI config of LAN 82540
U36 FWH symbol changed due to wrong pinout (Pin 23, 24 and 25)
R496 changed to 4k7 and set to GND (PD M66EN)
R525 and R499 is now populated
R530 not populated due to wrong V_2V5LAN voltage
U20.G4 is now 51R Pulldown to GND
U20.H4 is now 33R Pullup to V_3V3LAN
AC97 Fixup (AC_SDIN0 -> Changed to AC_SDIN2 on ICH4)
Swap ICH4 Pin N20 and P21 (H_HISTB+ / H_HISTB-) due to wrong info in yellow cover
LAN 82540 Fixup (R519 populated with 0R, R517 changed to 2K49 and R513 changed to 330R)
R615 changed to 4K32 due to Cougar Bug
HW Rev changed to 2 at Glue Logic
R373 is now populated with 10M
CN12.4 must be isolated cause of shortcut of AUD_MIC_BIAS to GND
PU R761-R765 added to VID[0:4]
PU R766 added to U23.15, PD R767 added to U23.14 (Panellink strapping options)
HD-LED-power connected to V_5V0 instead of V_5V0SB
PD R768 added to PS_ON
PU R769 added to U3.28 (PGOOD408#)
PD R770, R771, R772 added to power enables (default off, if CPLD not configured)
PD R773-R776 added to serial port shut down pins
Splitted SMI# and PME# signals of SIO0 and SIO1 on ICH4-GPIOs
Removed R383, R384, R385
Added D25 to avoid crossvoltages from VGA Monitor
Added D26 to avoid crossvoltages LPT Port
Alternative population of L7 to L12 with resistors (0R)
PME# Signal of Cougar (PinB7) is set to V_3V3 via 0R
U29 (LP3965EMP) can be replaced by an 0R_1206 to power 3V3 on Cougar
Possibility to PullDown Pin D8(MD24) on Cougar to enable SDRAM
CN41 (JUMPER 3x1) added to connect to MPCI Pins (TIP and RING)
V_5V0 input at V_DDR supply is now controlled by XILINX CPLD (Pin 25)
Delay of PWRGOOD# (LAN 82540EM Pin A9) to enable correct EEPROM detection
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THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER,
INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR
PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION
OR SAMPLE.
A
General Note:
All Parts marked 'XXX1' will not be assembled in V1.
All Parts marked 'XXX2' will not be assembled in V2.
No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted herein. Intel disclaims all
liability, including liability for infringement of any proprietary rights,
relating to use of information in this specification. Intel does not
warrant or represent that such use will not infringe such rights.
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE OR THE
MISUSE OF THIS INFORMATION.
* Other names and brands may be claimed as the property of others.
Intel (R) 845E Interactive Client Reference Design
Title
Size
A
COVER SHEET
Document Number
C
Date
B444B-W
Sheet
1
Rev
2.00
1
of
35
Friday, September 26, 2003
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Block Diagram
D
D
CPU VRM
Pg. 35
CPU
Clocking
ICS950201
CK 408
Pg. 12
Glue Logic
Xilinx *
Coolrunner
Pg. 18
- Postcode decoding
- Speedstep logic
- Powerup sequencing
ITP
Pg. 8
Pentium(R) 4 Processor
FCPGA478
Pg. 6, 7
FSB 133MHz x4, 64b (4.3 GB/s)
1280x1024 @ 18Bit
LVDS
Pg. 27
planar
C
max. 2 GB
DDR-DIMM
Cougar 3DR *
DVI/VGA
845E MCH
C
DVI-I
Pg. 27
I/O panel
BGA385
16 MB int. mem.
Pg. 26, 27, 28
AGP 1.5V, 66MHz x4, 32b (1.1 GB/s)
i82845-E
BGA593
DDR SDRAM 2.5V, 266MHz, 64b (2.1 GB/s)
DDR VR
Pg. 34
TV-OUT
Pg. 27
I/O panel
Pg. 9, 10, 11
PHY
RJ45
Pg. 31
I/O panel
PCI, 33MHz, 32b (132 MB/s)
Pg. 13
Pg. 14
Hub Interface 66MHz x4, 8b (266 MB/s)
i82562
Pg. 31
ICH4
i82801
BGA421
LPC 3.3V, 33MHz
B
B
5V PCI-Slot
Pg. 29
miniPCI-Slot
Pg. 29
LAN
i82540
(optional
i82551/i82559)
Pg. 24, 25
Pg. 15, 16, 17
SMB
SYSMON
LM87
Pg. 33
FAN
PHOTO DIODE
FWH
8 Mbit
i82802AC
PLCC32
Pg. 33
SIO
LPC47N227
SIO
LPC47M107
RJ45
Pg. 25
I/O panel
ATA66/100
Pg. 20
Pg. 19
USB2.0
AC'97
Pg. 22
SERIAL2
SERIAL0
SERIAL1
FDD
PARALLEL
K/B
MOUSE
I/O panel
I/O panel
planar
I/O panel
planar
planar
Pg. 21
Pg. 21
Pg. 30
Pg. 21
Pg. 22
Pg. 22
A
IDE0
Pg. 30
planar
USB
Pg. 31, 32
AC97
AD1885
LINE-IN
LINE-OUT
HEADPHONE
MICRO
I/O panel
planar
I/O panel
I/O panel
planar
Pg. 22
SERIAL3
Pg. 20
FIR
3 * planar
IDE1
Pg. 30
planar
A
2 * I/O panel
2 * I/O panel, powered
2 * planar
Pg. 23
CD-ROM
Intel (R) 845E Interactive Client Reference Design
Title
Size
BLOCK-DIAGRAM
Document Number
C
Date
5
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3
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B444B-W
Sheet
1
Rev
2.00
2
of
35
Friday, September 26, 2003
5
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1
SLP_S3#
ATX POWER
D
ATX 12V
12V
D
12V
5V 5VSB 3V3
CPU
VRM MODULE
MIC5284
VCCP
VCC_1V2VID
CLK
VCC_CLK
MCH
VTT
C
ISL6225 A
LTC1117
VCC_1V5
VCC_1V8
VCC_DDR
C
DIMM
ISL6225 A
SLP_S4#
VCC_REF
SLP_S3#
VCC_DDR
B
VCC_TERM
B
ICH4
VCC_5V0SUS
B
LTC1117
LTC1117
VCC_3V3SUS
VCC_1V5SUS
VCC_1V8S
VCC_1V5S
VCC_3V3S
VCC_5V0S
A
A
COUGAR *
ISL6225
B
V_3V3AGP
Intel (R) 845E Interactive Client Reference Design
Title
Size
BLOCK-POWER
Document Number
C
Date
5
4
3
2
B444B-W
Sheet
1
Rev
2.00
3
of
35
Friday, September 26, 2003
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Mx
Mx
Mx
B1
BOHR4.0
B4
BOHR4.0
B7
BOHR4.0
M29
M10
M7
M1
Mx
Mx
1
2
3
MACADRESS
B3
BOHR4.0
B9
BOHR4.0
82802AC
M30
BRD1
BIOS IN
Firmware-Hub
P4_RETENT
M2
M23
SM02/RD
M24
SM02/RD
M25
SM02/RD
M26
SM02/RD
Mx
Mx
MACADRESS
XXX1
XXX2
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
B444B
PCB
M31
M E C H
DK1
DK2
DK3
DK4
DK5
DK204060 DK204060 DK204060 DK204060 DK204060
BAT_CR2032
M11
M32
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
M E C H
JMP_2mm54
HS_MCH_PIN_FIN
XXX1
XXX2
M15
HS_MCH_LEVER
XXX1
XXX2
HS_MCH_INTERFACE
XXX1
XXX2
M16
1
2
3
4
5
6
7
8
BGA593A/COOL
M12
4
D
Mx
B2
BOHR4.0
B5
BOHR4.0
B8
BOHR4.0
FWH
B4441000.01
D
M17
DK6
DK7
DK8
DK9
DK10
DK204060 DK204060 DK204060 DK204060 DK204060
HS_MCH_CLIP HS_MCH_PORON
XXX1
XXX1
XXX2
XXX2
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
C
C
DK11
DK12
DK13
DK14
DK15
DK204060 DK204060 DK204060 DK204060 DK204060
V_CORE
V_CORE
V_CORE
DK16
DK17
DK18
DK204060 DK204060 DK204060
MARKE1
MARKETOP
MARKE2
MARKETOP
MARKE3
MARKETOP
MRKF1
MARKFPIT
B
B
TP1
TP2
TP3
TP4
GND
GND
GND
GND
A
A
Intel (R) 845E Interactive Client Reference Design
Title
6..8,11,17,33,35
V_CORE
V_CORE
MECH-ROUTE
Document Number
Size
C
Date
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INPUT
VOLTAGES
V_12V0VRM
V_12V0
D
DERIVED VOLTAGES -->
V_12V0VRMF
V_FAN1
V_FAN1S
V_FAN1SF
V_FAN2
V_FAN2S
V_FAN2SF
V_3V3SB
V_1V5SB
V_KB
V_KBF
V_DDR
V_USB0
V_USB1
V_USB2
V_USB3
V_USB4
V_USB5
V_1V5
V_USB0X
V_USB1X
V_USB2X
V_USB3X
V_USB4X
V_USB5X
V_DDRVTT
V_DDRREF
V_12USB2
V_12USB2F
V_12USB2S
V_12USB3
V_12USB3F
V_12USB3S
V_12VAUD
V_AUDOUT
V_5VAUD
V_BLI
V_CORE
V_VCCA
V_VCCIOPLL
I2C DEVICES
DEVICE
CLOCK GENERATOR
SO-DIMM0
SO-DIMM1
ICH4 SLAVE
LAN CONTROLLER
LM87 HW MONITOR
ADDRESS
1101001x
1010000x
1010001x
1000100x
N/A
0101110x
BUS
SM
SM
SM
SM
SM
SM
BUS
BUS
BUS
LINK
LINK
BUS
D
V_5V0SB
V_3V3LAN
V_3V3LAN0
V_1V5LAN
V_2V5LAN
PCI/AGP DEVICES
DEV
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
IDSEL
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
DEVICE
COUGAR AGP
LAN10/100/1000T
IRQ
A
G
REQ/GNT
AGP
4
V_5V0
C
V_1V5A1
V_1V5A2
V_2V5_LVD
V_HVDD
V_ICHPLL
V_2V5_LVD1 V_PLLVDD
V_2V5_LVD2
V_LVDD1
V_CVDD
V_LVDD2
V_VDD1
INTERNAL LAN
MINI PCI SLOT
STD PCI SLOT
RISER SLOT1
RISER SLOT2
RISER SLOT3
N/A
E-F
A-B-C-D
B-C-D-A
C-D-A-B
D-A-B-C
N/A
3
0
0
1
2
C
V_3V3AGP
V_2V0_2V5
V_2V5_VDD
V_VCC1
V_AVCC1
V_PVCC1
V_VREF_SII
V_DBL
V_5DVI
V_PIDE
V_SIDE
V_FIR
V_IR
V_3V3
V_1V2VID
V_1V8
V_CLK
V_5V0CF
V_5DVIF
V_IOLAN
V_GAME
V_GAMEF
V_AMP
V_AMPIN
V_AMPINX
V_AMPOUT
V_5V0REF
V_DL_CL
V_DL_CLF
V_AVDD
V_FPVDD
V_TVDD
V_VPVDD
ICH4 GPIOs
V_VDD2
V_VDD3
GPIO
GPI6
GPI7
GPI8
GPI12
GPI13
GPIO25
GPIO27
GPIO28
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43
DEVICE
SUPER I/O 0
SUPER I/O 1
SUPER I/O 0
SUPER I/O 1
CPLD
LAN0 KINNERETH
MINI PCI
CPLD
PRIMARY IDE
SECONDARY IDE
POWERED USB
POWERED USB
FIRMWARE HUB
FIRMWARE HUB
PCI RISER
PCI RISER
AUDIO AMPLIFIER
PCI RISER
PCI SLOT
PCI SLOT
SIGNAL NAME
SIO0_SMI#
SIO1_SMI#
SIO0_PME#
SIO1_PME#
XC_GPIO2
LAN0_ENA
MPCI_ACT#
XC_GPIO1
IDE_PPDIAG#
IDE_SPDIAG#
USB_PWR2ENA#
USB_PWR3ENA#
FWH_WP#
FWH_TBL#
RISER_ID1
RISER_ID2
AMP_SHDN
NOGO
P_PRSNT1#
P_PRSNT2#
B
B
V_3V3SB
V_RTC
V_BAT
V_RTCBIAS
V_-12V0
V_-5V0
POWER STATES
A
A
ON IN STATE
S5 (SOFT OFF)
S3 (SUS. TO RAM)
S0 (FULL ON)
5
POWER PLANE
V_*SB, V_KB, V_*LAN, V_USB*
Intel (R) 845E Interactive Client Reference Design
V_DDR, V_DDRREF
Title
OTHERS
4
3
2
NOTES
Document Number
Size
C
Date
B444B-W
Sheet
1
Rev
2.00
5
of
35
Friday, September 26, 2003

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