Acer Aspire 4253_5253_Compal_LA-7092P_JE50_HM50_SJV50_BZ_P5WE6_P5WH6_P5WS6_Rev1.0.pdf

(1596 KB) Pobierz
A
B
C
D
E
1
1
Compal Confidential
2
JE50/HM50/SJV50_BZ
P5WE6/P5WH6/P5WS6 Schematics Document
AMD Brazos
Brazos with Zacate / Hudson M1 / Seymour XT
2
3
DIS only / UMA only / PX Muxless / PX Muxless with BACO
3
2010-11-16
LA-7092P REV: 1.0
ZZZ
PCB
Part Number = DAZ0IC00100
4
4
Security Classification
Issued Date
2010/08/20
Compal Secret Data
Deciphered Date
2011/08/20
Title
Compal Electronics, Inc.
Cover Page
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
LA-7092P P5WE6/H6/S6
Tuesday, November 16, 2010
E
Rev
1.0
of
47
Date:
Sheet
1
A
B
C
D
E
Compal Confidential
Model Name : P5WE6/P5WH6/P5WS6
JE50/HM50/SJV50_BZ
PCB PN : DAZ0IC00100
VRAM 512M/1G
64M16/128M16 x 4
page 23
1
DDR3
ATI Vancuver Seymour
uFCBGA-962
Thermal Sensor
ADM1032
page 19
Page 18,19,20,21,22
Brazos
Memory BUS(DDR3)
Single Channel
1
204pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
page 8,9
PCI-Express x 4
Gen2
DP0
AMD Brazos APU
FT1
BGA 413-Ball
19mm x 19mm
page 5,6,7
1.5V DDRIII 800~1066MHz
LVDS
page 10
DP1
2
CRT
page 12
2
USB port 0,1,2
USB port 5
USB port 7
USB port6
USB port 8
HDMI
Conn.
page
UMI Gen.1 x4
PCI-Express
2.5GT/s per lane
USB
Conn x 3
page 33
CMOS
Camera
page 10
Bluetooth
Conn
page 33
Card
Reader
RT5137
page 29
Mini
card
(WL)X1
page 29
11
FCH
Hudson-M1
BGA 605-Ball
23mm x 23mm
LED
3
3.3V 48MHz
3.3V 24.576MHz/48Mhz
USB
HD Audio
S-ATA
Gen2
MINI Card
WLAN
page 29
LAN(GbE)
Atheros
AR8151
page 26
page 13,14,15,16,17
page 32
HDA Codec
CX20584
27
page
LPC BUS
SATA HDD
Conn.
page 30
port 0
3
GPP3
GPP2
RTC CKT.
page 13
RJ45
page 26
SATA ODD
Sub/B
page
port 1
30
Power On/Off CKT.
page 34
ENE KB930
page 31
MIC Jack x 1
HP Jack x 1
Int MIC x 1
Int SPK x 1
page 28
VGA
Power sequence
DC/DC
page 24,25
Touch Pad
Fan Control
Int.KBD
page 32
page 32
4
DC/DC Interface CKT.
page 35
page 34
EC I/O Buffer
page 32
BIOS
page 32
4
Power Circuit
page 36,37,38,39,40,41
42,43,44,45
Extend Card/B
1. USB X2
2. ODD X1
B
Security Classification
Issued Date
2010/08/20
Compal Secret Data
Deciphered Date
2011/08/20
Title
Compal Electronics, Inc.
Block Diagrams
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
LA-7092P P5WE6/H6/S6
Monday, November 15, 2010
E
Rev
1.0
of
47
Date:
Sheet
2
A
A
B
C
D
E
Voltage Rails
Power Plane
VIN
B+
+VSB
+3VALW
1
Description
Adapter power supply (19V)
AC or battery power rail for power circuit.
VSB always on power rail
3.3V always on power rail
5V always on power rail
1.1V always on power rail
Core voltage for CPU (0.7-1.2V)
1.0V switched power rail
1.5V power rail for CPU VDDIO and DDRIII
0.75VS switched power rail for DDR terminator
1.05V switched power rail for APU VDD10
1.1VS switched power rail
1.8V switched power rail
3.3V switched power rail
5V switched power rail
Core voltage for GPU
3.3V switched power rail for GPU
1.8V switched power rail for GPU
1.5V switched power rail for GPU
1.0V switched power rail for GPU
3.3V power rail for LAN
RTC power
S1
N/A
N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
S3
N/A
N/A
ON
ON
ON
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
S5
N/A
N/A
ON*
ON*
ON*
ON*
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
SIGNAL
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
+VALW
ON
ON
ON
ON
ON
+V
ON
ON
ON
OFF
OFF
+VS
ON
ON
OFF
OFF
OFF
Clock
ON
LOW
OFF
OFF
OFF
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
+5VALW
+1.1VALW
+APU_CORE
+APU_CORE_NB
+1.5V
+0.75VS
+1.05VS
+1.1VS
+1.8VS
+3VS
+5VS
+VGA_CORE
+3VSG
+1.8VSG
+1.5VSG
+1.0VSG
1
Board ID / SKU ID Table for AD channel
Vcc
Ra/Rc/Re
Board ID
0
1
2
3
4
5
6
7
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
Project ID Table
V
AD_BID
min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V
AD_BID
typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V
AD_BID
max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
Board ID
0
1
2
3
4
5
6
7
PCB Revision
2
+3V_LAN
+RTCVCC
2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table
EC SM Bus1 address
Device
Address
HEX
BTO Option Table
PCB Revision
w/ X'tal X1
wo/ X'tal X1
EC SM Bus2 address
Device
ADM1032 (GPU)
Address
1001-101xb
HEX
9AH
SM Bus Controller 0
Device
3
(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)
Board ID
0
1
2
3
4
5
6
7
Address
HEX
APU SIC/SID (FCH_SMB3)
H_THERMTRIP# (FCH_ALERT#)
Project ID Table
(FCH_SMB0)
SM Bus Controller 1
Device
DDR DIMM1 (FCH_SMB0)
DDR DIMM2 (FCH_SMB0)
WLAN (FCH_SMB0)
Address
1001-000xb
1001-001xb
HEX
90
92
Board ID
0
1
2
3
4
5
6
7
PCB Revision
BTO Item
BOM Structure
Display from APU
UMA@
Display from VGA
DISO@
Use VGA
VGA@
Muxless w/BACO
BACO@
Muxless wo/BACO
WOBACO@
Muxless
PX@
VAN@
w/Vancouver Serise
w/Manhttan Serise
MAN@
Bluetooth
BT@
AR8151
8151@
Seymour
Seymour@
wo/Muxless
WOPX@
wo/VGA
WOVGA@
APU 1.5G
15G@
APU 1.6G
16G@
3
*UMA only :
UMA@ BT@ 8151@ WOVGA@ WOPX@
VGA Chip SEL:
1. Seymour@ + Van@
2. Robson@ + Man@
APU Chip SEL:
1. 16G@
2. 15G@
4
*DIS only :
VGA@ DISO@ WOBACO@ BT@ 8151@ WOPX@
*Muxless w/BACO :
UMA@ VGA@ PX@ BACO@ BT@ 8151@
Muxless wo/BACO :
UMA@ VGA@ PX@ WOBACO@ BT@ 8151@
4
Security Classification
Issued Date
2010/08/20
Compal Secret Data
Deciphered Date
2011/08/20
Title
Compal Electronics, Inc.
Notes List
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
LA-7092P P5WE6/H6/S6
Tuesday, November 16, 2010
E
Rev
1.0
of
47
Date:
Sheet
3
5
4
3
2
1
Power-Up/Down Sequence
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.
2. VDDR3 should ramp-up before or simultaneously with VDDC.
D
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).)
D
VDDR3(3.3VSG)
PCIE_VDDC(1.0V)
C
Note: Do not drive any IOs before VDDR3 is ramped up.
VDDR1(1.5VSG)
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
PE_GPIO0
PE_EN
C
PERSTb
PE_GPIO1
BIF_VDDC
REFCLK
B
PX_mode
B
Straps Reset
Straps Valid
Global ASIC Reset
MOS
SI4800
Regulator
Regulator
SI4800
T4+16clock
PWRGOOD
A
A
Security Classification
Issued Date
2010/08/20
Compal Secret Data
Deciphered Date
2011/08/20
Title
Compal Electronics, Inc.
dGPU Block Diagram
Document Number
Rev
1.0
of
47
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
LA-7092P P5WE6/H6/S6
Monday, November 15, 2010
Sheet
1
Date:
4
5
4
3
2
1
+1.8VS
<11> APU_HDMI_TX2P
<11> APU_HDMI_TX2N
R399
R400
R142
R401
R402
R141
1
1
2
2
1
1
2
2
1
1
2
2
1K_0402_5%
1K_0402_5%
300_0402_5%
300_0402_5%
510_0402_1%
1K_0402_5%
APU_SVC
APU_SVD
APU_RST#
APU_PWRGD
TEST_25_L
TEST36
<11> APU_HDMI_TX1P
<11> APU_HDMI_TX1N
<11> APU_HDMI_TX0P
<11> APU_HDMI_TX0N
<11> APU_HDMI_CLKP
<11> APU_HDMI_CLKN
C237
0.01U_0402_25V7K
APU_RST#
1 @ 2
C238
0.01U_0402_25V7K
APU_PWRGD
@ 2
1
<10> APU_TXOUT2+
<10> APU_TXOUT2-
<10> APU_TXOUT1+
<10> APU_TXOUT1-
<10> APU_TXOUT0+
<10> APU_TXOUT0-
2
1K_0402_5%
APU_PROCHOT#
APU_CRT_DDC_SCL
APU_CRT_DDC_SDA
APU_ALERT#_R
APU_SIC
APU_SID
<13> APU_CLKP
<13> APU_CLKN
<13> APU_DISP_CLKP
<13> APU_DISP_CLKN
<44> APU_SVC
<44> APU_SVD
APU_SIC
APU_SID
<13> APU_RST#
<13> APU_PWRGD
<31> EC_THERM#
<13> FCH_PROCHOT#
R169
1
R168
1
@
2
0_0402_5%
2
0_0402_5%
<10> APU_TXCLK+
<10> APU_TXCLK-
A8
B8
B9
A9
D10
C10
A10
B10
B5
A5
D6
C6
A6
B6
D8
C8
V2
V1
D2
D1
J1
J2
P3
P4
T3
T4
APU_PROCHOT#
U1
APU_THERMTRIP#
U2
APU_ALERT#_R
T2
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
N2
N1
P1
P2
M4
M3
M1
F4
G1
F3
F1
B4
W11
V5
+3VS
U22B
DISPLAYPORT 1
DP MISC
TDP1_TXP0
TDP1_TXN0
TDP1_TXP1
TDP1_TXN1
TDP1_TXP2
TDP1_TXN2
TDP1_TXP3
TDP1_TXN3
LTDP0_TXP0
LTDP0_TXN0
LTDP0_TXP1
LTDP0_TXN1
LTDP0_TXP2
LTDP0_TXN2
LTDP0_TXP3
LTDP0_TXN3
CLKIN_H
CLKIN_L
DP_ZVSS
DP_BLON
DP_DIGON
DP_VARY_BL
TDP1_AUXP
TDP1_AUXN
TDP1_HPD
H3
G2
H2
H1
B2
C2
C1
A3
B3
D3
C12
D13
A12
B12
A13
B13
E1
E2
F2
D4
D12
R1
R2
R6
T5
E4
K4
L1
L2
M2
K1
K2
L5
M5
M21
J18
J19
U15
T15
H4
N5
R5
R398
1
2
150_0402_1%
APU_ENBKL <10>
APU_ENVDD <10>
APU_BLPWM <10>
D
D
APU_HDMI_CLK
APU_HDMI_DATA
APU_HDMI_CLK <11>
APU_HDMI_DATA <11>
APU_HDMI_HPD <11>
DISPLAYPORT 0
LTDP0_AUXP
LTDP0_AUXN
LTDP0_HPD
DAC_RED
DAC_REDB
DAC_GREEN
DAC_GREENB
DAC_BLUE
DAC_BLUEB
DAC_HSYNC
DAC_VSYNC
DAC_SCL
DAC_SDA
DAC_ZVSS
APU_LCD_CLK
APU_LCD_DATA
R406
1
R407
1
R408
1
R409
1
2
100K_0402_5%
2
150_0402_1%
2
150_0402_1%
2
150_0402_1%
APU_LCD_CLK <10>
APU_LCD_DATA <10>
APU_CRT_R <12>
APU_CRT_G <12>
APU_CRT_B <12>
APU_CRT_HSYNC <12>
APU_CRT_VSYNC <12>
APU_CRT_DDC_SCL <12>
APU_CRT_DDC_SDA <12>
+3VS
R410
1
R109
1 UMA@ 2
4.7K_0402_5%
R155
1 UMA@ 2
4.7K_0402_5%
R411
1
R143
1
R414
1
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
For DVT 1011
DISP_CLKIN_H
DISP_CLKIN_L
SVC
SVD
SIC
SID
RESET_L
PWROK
PROCHOT_L
THERMTRIP_L
ALERT_L
TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L
CLK
VGA DAC
R144
1
2
499_0402_1%
PAD T66
PAD T67
SER
C
T93PAD
T94PAD
Close to APU
<44> APU_VDDNB_RUN_FB_H
<44> APU_VDD0_RUN_FB_H
T77PAD
<44> APU_VDD0_RUN_FB_L
VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE
VSS_SENSE
RSVD_1
RSVD_2
RSVD_3
ONTARIO-2M161000-1.6G_BGA413
15G@
TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
TEST33_H
TEST33_L
TEST34_H
TEST34_L
TEST35
TEST36
TEST37
TEST15
TEST18
TEST19
TEST25_H
TEST_25_L
PAD T68
R415
1
R416
1
R417
1
R418
1
@
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
510_0402_1%
C
CTRL
TEST
TEST31
PAD T73
TEST33_H
C516
R420
1
1
2
0.1U_0402_16V4Z
TEST33_L
C517
R421
1
1
2
0.1U_0402_16V4Z
Delete Test point for layout limitation
20100917
TEST35
R422
1
@
2
1K_0402_5%
TEST36
TEST37
R958
1
2
1K_0402_5%
PAD T76
+1.8VS
JTAG
2
51_0402_1%
2
51_0402_1%
TEST38
DMAACTIVE_L
K3
T1
R423
1
2
1K_0402_5%
ALLOW_STOP# <13>
+1.8VS
APU : SA00004DO60 (S IC ZACATE 2M151132B1240 1.5G BGA)
R424
10K_0402_5%
1
APU : SA000046G80 (S IC ZACATE 2M161232B2240 1.6G BGA )
U22
16G@
B
2
1K_0402_5%
1
E
APU_THERMTRIP#
2
B
B
R425
2
3
Q79
1
AMD Debug
H_THERMTRIP# <14>
Zacate FT1 B0
+1.8VS
+1.8VS
JHDT1
1
1K_0402_5%
2
3
5
7
0_0402_5%
R846
1
2
R847
2
R176
2
R177
2
APU_TRST#_R
9
11
13
15
17
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
APU_TCK
APU_TMS
APU_TDI
APU_TDO
APU_PWRGD
+1.8VS
APU_RST#
APU_DBRDY
APU_DBREQ#
J108_PLLTST0
J108_PLLTST1
R178
1
R799
1
R863
1
2
300_0402_5%
2
0_0402_5%
2
0_0402_5%
TEST19
TEST18
R843
2
R840
2
R798
2
1
1K_0402_5%
1
1K_0402_5%
1
1K_0402_5%
MMBT3904_NL_SOT23-3
1
R427
@
2
0_0402_5%
CPU TSI interface level shift
@
C236
1
@
1
R428
2
@
1
R160
2
0.1U_0402_10V7K
2
R842
1
If FCH internal pull-up disabled, level-shifter could be deleted.
Need BIOS to disable internal pull-up!!
C
C
APU_TRST#
+3VS
BSH111, the Vgs is:
min = 0.4V
Typ = 1.0V
Max = 1.3V
FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V
If use level shift, EC_SMB need pull up
(pop R747 & R748)
FCH_SID <14>
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
31.6K_0402_1%
2
G
APU_SID
3
30K_0402_1%
1.607V for Gate
EC_SMB_DA
1
@
Q22
BSH111 1N_SOT23-3
D
1
R431
2
0_0402_5%
@
1
R432
1
R433
@
1
R429
1
R430
19
A
FCH_SID
2
0_0402_5%
EC_SMB_DA2
2
0_0402_5%
Please be noted about TEST_18 and TEST_19
T0 FCH
TO EC
EC_SMB_DA2 <19,31>
SAMTE_ASP-136446-07-B
CONN@
A
2
APU_SIC
3
S
S
EC_SMB_CK
1
@
Q23
BSH111 1N_SOT23-3
D
1
R434
5
G
FCH_SIC
2
0_0402_5%
EC_SMB_CK2
2
0_0402_5%
FCH_SIC <14>
T0 FCH
TO EC
Security Classification
Issued Date
2010/08/20
Compal Secret Data
Deciphered Date
2011/08/20
Title
Compal Electronics, Inc.
FT1 CTRL/DP/CRT
Rev
1.0
5
of
47
Sheet
1
EC_SMB_CK2 <19,31>
2
0_0402_5%
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7092P P5WE6/H6/S6
Date:
Wednesday, November 24, 2010
3
2

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