Apple_IMAC 5.2_VALLCO_051-7199_RevA.pdf

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8
7
6
5
4
3
REV
2
ZONE
ECN
DESCRIPTION OF CHANGE
1
CK
APPD
ENG
APPD
DATE
06/22/04
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
IMAC 5,2 -- REV A
7/25/06
DATE
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
01/05/2006
01/05/2006
01/05/2006
MASTER
01/05/2006
MASTER
01/05/2006
01/05/2006
(MASTER)
01/05/2006
01/05/2006
MASTER
MASTER
DATE
A
451207
PRODUCTION RELEASED
07/26/06
D
PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
SYNC MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
M38
M1
PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
SYNC MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
M1
(MASTER)
M38
MASTER
M38
MASTER
MASTER
M38
DATE
MASTER
MASTER
MASTER
MASTER
MASTER
D
2
TABLE_TABLEOFCONTENTS_ITEM
2
3
4
5
6
7
8
9
10
11
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18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
34
38
41
42
43
System Block Diagram
Power Block Diagram
Table Items
FUNC TEST 1 OF 2
Power Conn / Alias
CPU 1 OF 2-FSB
CPU 2 OF 2-PWR/GND
CPU DECAPS & VID<>
CPU TEMP SENSOR
CPU ITP700FLEX DEBUG
NB CPU Interface
NB Misc Interfaces
NB DDR2 Interfaces
NB Power 1
NB Power 2
NB Grounds
NB (GM) Decoupling
NB Config Straps
SB: 1 OF 4
SB: 2 OF 4
SB: 3 OF 4
SB: 4 OF 4
SB:DECOUPLING
SB: MISC
SB: SMB HUB AND ALIAS
38
TABLE_TABLEOFCONTENTS_ITEM
44
45
46
47
53
54
58
59
60
61
63
65
66
67
68
72
73
74
75
76
77
78
79
80
82
83
94
95
96
97
FW: FW323-06
FW: DECAPS
FIREWIRE CONNECTORS
USB Device Interfaces
AIRPORT CONN
PCIE PORT ALIASES
SMC
SMC & TPM SUPPORT
LPC+ CONN
NB THERMAL
SPI BOOTROM
Fan 0, 1 & System Temp
Fan 2 & HD Temp
TPM
AUDIO: CODEC
3
TABLE_TABLEOFCONTENTS_ITEM
39
TABLE_TABLEOFCONTENTS_ITEM
4
TABLE_TABLEOFCONTENTS_ITEM
40
TABLE_TABLEOFCONTENTS_ITEM
5
TABLE_TABLEOFCONTENTS_ITEM
41
TABLE_TABLEOFCONTENTS_ITEM
6
TABLE_TABLEOFCONTENTS_ITEM
42
TABLE_TABLEOFCONTENTS_ITEM
7
TABLE_TABLEOFCONTENTS_ITEM
43
TABLE_TABLEOFCONTENTS_ITEM
8
TABLE_TABLEOFCONTENTS_ITEM
44
TABLE_TABLEOFCONTENTS_ITEM
9
TABLE_TABLEOFCONTENTS_ITEM
45
TABLE_TABLEOFCONTENTS_ITEM
10
TABLE_TABLEOFCONTENTS_ITEM
46
TABLE_TABLEOFCONTENTS_ITEM
11
TABLE_TABLEOFCONTENTS_ITEM
47
TABLE_TABLEOFCONTENTS_ITEM
C
12
TABLE_TABLEOFCONTENTS_ITEM
48
TABLE_TABLEOFCONTENTS_ITEM
13
TABLE_TABLEOFCONTENTS_ITEM
NB PEG / Video Interfaces
M1
MASTER
M1
MASTER
M40
M1
(MASTER)
M1
M38
MASTER
MASTER
M38
MASTER
MASTER
MASTER
49
TABLE_TABLEOFCONTENTS_ITEM
14
TABLE_TABLEOFCONTENTS_ITEM
50
TABLE_TABLEOFCONTENTS_ITEM
15
TABLE_TABLEOFCONTENTS_ITEM
51
TABLE_TABLEOFCONTENTS_ITEM
16
TABLE_TABLEOFCONTENTS_ITEM
52
TABLE_TABLEOFCONTENTS_ITEM
17
TABLE_TABLEOFCONTENTS_ITEM
53
TABLE_TABLEOFCONTENTS_ITEM
AUDIO: SPEAKER AMP
AUDIO: CONNECTORS
18
TABLE_TABLEOFCONTENTS_ITEM
54
TABLE_TABLEOFCONTENTS_ITEM
19
TABLE_TABLEOFCONTENTS_ITEM
55
TABLE_TABLEOFCONTENTS_ITEM
AUDIO: POWER SUPPLIES
20
TABLE_TABLEOFCONTENTS_ITEM
56
TABLE_TABLEOFCONTENTS_ITEM
IMVP6 CPU VCore Regulator
ASTER
M
PWR GOOD
21
TABLE_TABLEOFCONTENTS_ITEM
B
22
TABLE_TABLEOFCONTENTS_ITEM
23
TABLE_TABLEOFCONTENTS_ITEM
24
TABLE_TABLEOFCONTENTS_ITEM
01/05/2006
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
25
TABLE_TABLEOFCONTENTS_ITEM
26
TABLE_TABLEOFCONTENTS_ITEM
27
TABLE_TABLEOFCONTENTS_ITEM
28
TABLE_TABLEOFCONTENTS_ITEM
DDR2 SO-DIMM Connector A
MASTER
DDR2 SO-DIMM Connector B
MASTER
Memory Active Termination
MASTER
Memory Vtt Supply
CLOCKS
CLOCKS:
TERMINATIONS
Disk Connectors
ETHERNET CONTROLLER
ETHERNET MISC
ETHERNET CONNECTOR
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
29
TABLE_TABLEOFCONTENTS_ITEM
30
TABLE_TABLEOFCONTENTS_ITEM
31
TABLE_TABLEOFCONTENTS_ITEM
32
A
TABLE_TABLEOFCONTENTS_ITEM
33
TABLE_TABLEOFCONTENTS_ITEM
P
e
r
57
58
59
60
61
62
63
64
65
66
67
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
CPU & SYSTEM SENSE CIRCUITRIES
(MASTER)
(MASTER)
(MASTER)
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
3V DC/DC 2.5V
1.8V & 1.2V VREG
5V DC/DC
1.5V_S0 & 1.05V_S0 VREG
S0 AND S3 FETS
Internal Display Conns
EXTERNAL TMDS
TMDS/Inverter/ExtVGA
External Display Conns
m
i
l
AUDIO
AUDIO
AUDIO
AUDIO
a
n
i
MASTER
01/05/2006
(MASTER)
12/09/2005
MASTER
01/05/2006
MASTER
MASTER
01/05/2006
05/12/2006
05/12/2006
05/12/2006
05/12/2006
MASTER
(MASTER)
(MASTER)
(MASTER)
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
X.XXX
ANGLES
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
y
r
METRIC
Apple Computer Inc.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
DESIGN CK
MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
C
B
DRAFTER
A
34
TABLE_TABLEOFCONTENTS_ITEM
ENG APPD
35
TABLE_TABLEOFCONTENTS_ITEM
QA APPD
DESIGNER
TITLE
36
TABLE_TABLEOFCONTENTS_ITEM
RELEASE
SCALE
NONE
SIZE
DRAWING NUMBER
SCHEM VALLCO
D
37
TABLE_TABLEOFCONTENTS_ITEM
MATERIAL/FINISH
NOTED AS
APPLICABLE
051-7199
SHT
REV.
A
OF
97
1
8
7
6
5
4
3
2
1
8
7
6
J0700
5
CPU
PAGE 7
J1101
(1.83/2.17GHZ)
CORE (~1.2V)
PAGE 8
4
ITP
CONN
PAGE 11
3
2
1
J9700
J9402
MINI-DVI
(TMDS - VGA)
LVDS
(INTERNAL)
PAGE 94
64-BIT
FSB
667MHZ
D
PAGE 94
D
J2800
J2900
VGA FOR DEBUG
PAGE 12
VIDEO
PAGE
13
6DUAL CHANNEL LVDS - 6BIT
NB- GT
CORE (1.50V)
PAGE 16-17
PAGE 15
U1200
DDR2 - DUAL CHAN
1.8V/667MHZ
64-BIT
DIMM
PARALLEL
TERM
PAGES 30
PAGE 28-29
MISC
PAGE 14
DMI
PAGE 14
4-BIT
DMI
1.2V/800MHZ
CONTROL = 2.5V
J2901 ALS+ATS TSENS
U1000 CPU TSENS
U6100 GPU+NB TSENS
C
U6300/01
J6601 HD TSENS
J6602 ODD TSENS
SPI
BOOTROM
PAGE 63
RMT MLB
FAN
J6500,J6501,J6600 FAN CONNS
U5800
JC900
LPC
DMI
SPI
PAGE 21
SATA
CONNECTOR
HARD DRIVE
PAGE 38
JC901
3.3V/66MHZ/133MHZ
OPTICAL
PAGE 38
B
X1 - 1.5GHZ
X1 - 1.5GHZ
J5300
U4101
MINI-PCIE
AIRPORT
YUKON
PAGE 41
GIG ETHERNET
A
PAGE 53
4 Diff pairs
JD600
P
e
r
FW323-06
FIREWIRE A
PAGE 44
0
1
2
PORT
#2-5
6
5
3,7
CORE (1.05V)
USB
UATA/66/100
PAGE 22
UATA
CONNECTOR
SB
J5300 (AIRPORT CONN)
IR
U2100
1 0,2,4
CAMERA
1.2V/1.5GHZ
PAGE 22
CORE
GPIOS
PAGE 23
PCI
AZALIA
PAGE 22
PAGE 21
PAGE 23
PAGE 24
m
i
l
TPM
PAGE 58
PAGE 67
PAGE 22
SMC
U6700
4-BIT (3.3V/33MHZ)
a
n
i
U3301
CK410
CLOCKS
PAGE 33
TERMS
PAGE 34
y
r
J4700
PAGE 47
3
7
MAIN MEMORY
C
J6000
LPC+ CONN
PAGE 60
JE310/JE320/JE330
JE350
USB
CONNECTORS
0
2
4
BNDI
INTERFACE
BT
CONN
PAGE 48
SMB
PAGE 21
SATA2
SATA0
PAGE 21
PORT
#0
PAGE 47
JE000, JE001
SATA
UATA
PCI-E
B
PAGE 22
PORT
#1
J2800
J2900
DIMM’S
U3301
J5300
CK410M
AIRPORT
33MHZ
32-BIT
U6800
S/PDIF
AUDIO CODEC
STA9221
PAGE 68
PORT A
PORT C
PORT F
PORT B
OPTICAL OUT
J7303
COMBO OUT
CONNECTOR
PAGE 153
LINE OUT
System Block Diagram
J7301
2 Diff pairs
J7300
JE350
MIC IN
BNDI
INTERFACE
SPEAKER
AMP
PAGE 72
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
SPEAKER
CONNECTOR
PAGE 73
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
REV.
A
ETHERNET
CONNECTOR
PAGE 43
FIREWIRE A
CONNECTORS
PAGE 46
LINE IN
CONNECTOR
PAGE 73
APPLE COMPUTER INC.
D
SCALE
NONE
051-7199
SHT
A
97
2
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
AC/DC POWER SUPPLY
12V, 180W, 15A
S5
D
PPVCORE_CPU_S0
1.3V @ 36A
PAGE 75
CPU_CORE
PP1V05_S0
1.05V @ 5.4A
PAGE 80
CPU_FSB
NB_FSB
SB_CORE
NB_VTT
SB_CPU_IO
D
CPU_AVDD
NB_PCIE
SB_IO
NB_CORE
NB_GRAPHICS
ENET_CORE
NB_DRAM
DRAM_CORE
DRAM_IO
SB
LCD
FW
SMC
SPI_BOOTROM
SB
AUDIO(+VREG)
PP1V5_S0
1.50V @ 10.12A
PAGE 80
PP1V2_S3
1.21V @ 0.426A
PAGE 79
PP1V8_S3
1.81V @ 10A
PAGE 79
PP2V5_S5
2.5V @ 0.426A ???
PAGE 78
PP3V3_S5
3.35V @ 4.0A
PAGE 78
PP5V_S5
2.5V @ 0.9A
PAGE 82
PP1V8_S0
FET
PAGE 83
TMDS
PP2V5_S0
FET
PAGE 83
NB_GRAPHICS
TMDS
PP3V3_S3
FET
PAGE 83
PP3V3_S0
FET
PAGE 83
C
B
A
P
8
7
e
r
m
i
l
5
4
a
n
i
PP2V5_S3
2.5V @ ?A
PAGE 42
ENET
PP5V_S0
FET
PAGE 83
SB_GPIO
FANS
HARD DRIVE
AUDIO CODEC
ODD
AIRPORT
TMDS
CK410
ENET
TPM
BT
PP5V_S3
FET
PAGE 83
USB
FHB
IR
SB
ODD
HDD
TMDS
NB_GRAPHICS
y
r
PP5V_S5_AUDIO
2.5V @ 0.9A
PAGE 82
AUDIO(ALTERNATE)
FW
PP12V_S0
FET
PAGE 83
SPK_AMP
PANEL INVERTER
FAN
HDD
C
B
Power Block Diagram
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
REV.
A
APPLE COMPUTER INC.
D
SCALE
NONE
051-7199
SHT
A
97
3
OF
6
3
2
1
8
7
6
5
4
3
2
1
COMMON
TABLE_5_HEAD
TABLE_5_HEAD
OPS REQUESTED QUAL PARTS
TABLE_5_HEAD
PART#
511S0025
338S0298
QTY
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
IC,CPU-SKT,479BGA
IC,945GT,NORTHBRIDGE
IC,SB,652BGA
BAT,COIN,3V,220MAH,CR2032
IC,CY28445-5,CLK GEN,68PIN QFN
REFERENCE DESIGNATOR(S)
J0700
U1200
U2100
BT2600
U3301
U4101
U4102
U4400
U5800
U6700
U7500
CRITICAL
CRITICAL
BOM OPTION
TABLE_5_ITEM
PART#
051-7199
TABLE_5_ITEM
QTY
1
1
1
1
DESCRIPTION
PCB,SCHEM,MLB,M50
PCB,FAB,MLB,M50
EFI ROM,M50A
M50 MEROM CPU
REFERENCE DESIGNATOR(S)
SCH1
CRITICAL
BOM OPTION
TABLE_5_ITEM
PART#
155S0295
TABLE_5_ITEM
QTY
1
3
DESCRIPTION
CHOKE,COMMON_MODE,165OHM,4PIN
PCAP,120UF,16V,20%,ELEC
REFERENCE DESIGNATOR(S)
L9703
C6505,C6504,C6602
CRITICAL
CRITICAL
BOM OPTION
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL
TABLE_5_ITEM
820-1960
(335S0384)
TABLE_5_ITEM
MLB1
TABLE_5_ITEM
124-0359
CRITICAL
TABLE_5_ITEM
CRITICAL
D
(335S0382)
343S0385
742-0048
359S0101
338S0270
341S1797
338S0279
CRITICAL
CRITICAL
TABLE_5_ITEM
341T0042
337S3386
U6301
CPU
D
CRITICAL
MEROM
CRITICAL
TABLE_5_ITEM
IC,88E8053,GIGABIT ENET XCVR,64P QFN,NO
CRITICAL
TABLE_5_ITEM
IC,ENET LAN ROM
IC,FW32306,1394A LINK,TQFP
IC,SMC,M50
IC,TPM,TSSOP,28P
IC,CPU VREG,IMVP,TWO PHASE
CRITICAL
TABLE_5_ITEM
CRITICAL
TABLE_5_ITEM
338S0274
341T0022
341S1789
353S1461
CRITICAL
TABLE_5_ITEM
341S1859
337S3242
337S3280
IC EFI BOOTROM DEV M50
M38 CPU(C0)
M50 1.83G LOW SPEED CPU (D0)
CRITICAL
CRITICAL
TPM
TABLE_5_ITEM
USE BOM OPTION MEROM FOR MEROM PROCESSOR
C
ALTERNATE PARTS
TABLE_ALT_HEAD
MECHANICAL PARTS
PART#
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
126S0092
353S1381
378S0140
353S1461
124-0333
BOM OPTION
REF DES
COMMENTS:
603-9187
603-9186
725-0668
725-0720
825-6447
126S0091
353S1278
378S0141
353S1465
124-0338
C625
U5940
FACTORY SHORTAGE
TABLE_ALT_ITEM
SMC VREF
TABLE_ALT_ITEM
LED601,LED602,LED603
TABLE_ALT_ITEM
U7500
C7953,C7954
CPU VREG, OLD DIE,SCREENED PART
TABLE_ALT_ITEM
FOR SUPPLY
B
A
P
8
7
e
r
m
i
l
QTY
1
1
1
1
1
DESCRIPTION
REFERENCE DESIGNATOR(S)
HS2
HS1
SUBASSY, M50 NB HEATSINK
SUBASSY, M50 CPU HEATSINK
MYLAR WASHER
WASH1
CVR1
MYLAR BLACK LED CVR, M50
BARCODE LABEL, M50A
[EEE:WJ9]
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
a
n
i
TABLE_5_HEAD
y
r
Table Items
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
C
BOM OPTION
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
MEROM
B
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
REV.
A
APPLE COMPUTER INC.
D
SCALE
NONE
051-7199
SHT
A
97
4
OF
6
5
4
3
2
1
8
LAYOUT NOTE: PLACE NEAR J0700
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
7
LAYOUT NOTE: PLACE NEAR U1200
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7
12 7
6
PP631
PP632
PP633
PP634
PP635
PP636
PP637
PP638
PP639
PP640
PP641
PP642
PP643
PP644
PP645
PP646
PP647
PP648
PP649
PP650
PP651
PP652
PP653
PP654
PP655
PP656
PP657
PP658
PP659
PP660
PP661
PP662
PP663
PP664
PP665
PP666
PP667
PP668
1
SM
1
SM
PP
PP
5
41 34
41 34
4
LAYOUT NOTE: PLACE NEAR U4101
ENET_CLK100M_PCIE_P
ENET_CLK100M_PCIE_N
3
PLACE NEAR R1210 AND R1211
12
2
PP1200
1
A
A
A
SM-TP50-TOP
78 77 76 66 65 59 26 6
83 80 79
83 82 80 79 59 6
83 82 80 79 78 77 76 6
83 79 6
76 75 6
26 25 24 21
1
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
60 59 58
60 59 58
60 59 58
60 59 58
60 59 58
60 58
IN
IN
IN
IN
IN
IN
IN
D
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 7 5
12 11 7
FSB_A_L<6>
FSB_ADSTB_L<0>
FSB_A_L<27>
FSB_ADSTB_L<1>
FSB_D_L<0>
FSB_DSTBN_L<0>
FSB_DSTBP_L<0>
FSB_DINV_L<0>
FSB_D_L<16>
FSB_DSTBN_L<1>
FSB_DSTBP_L<1>
FSB_DINV_L<1>
FSB_D_L<41>
FSB_DSTBN_L<2>
FSB_DSTBP_L<2>
FSB_DINV_L<2>
FSB_D_L<59>
FSB_DSTBN_L<3>
FSB_DSTBP_L<3>
FSB_DINV_L<3>
FSB_LOCK_L
FSB_CPURST_L
CPU_INIT_L
CPU_A20M_L
CPU_IGNNE_L
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
FSB_CLK_CPU_P
FSB_CLK_CPU_N
PP600
PP601
PP602
PP603
PP604
PP605
PP606
PP607
PP608
PP609
PP610
PP611
PP612
PP613
PP614
PP615
PP616
PP617
PP618
PP619
PP620
PP621
PP622
PP623
PP624
PP625
PP626
PP627
PP628
PP629
PP630
1
SM
1
SM
PP
PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
21 7
21 7
21 7
21 7
21 7
21 7
21 7
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
12 7
12 7
12 7
12 7
12 7
12 7
12 7
12 7
12 7
34 7
34 7
OMIT
P4MM
OMIT
P4MM
FSB_A_L<6>
FSB_ADSTB_L<0>
FSB_A_L<27>
FSB_ADSTB_L<1>
FSB_D_L<0>
FSB_DSTBN_L<0>
FSB_DSTBP_L<0>
FSB_DINV_L<0>
FSB_D_L<16>
FSB_DSTBN_L<1>
FSB_DSTBP_L<1>
FSB_DINV_L<1>
FSB_D_L<41>
FSB_DSTBN_L<2>
FSB_DSTBP_L<2>
FSB_DINV_L<2>
FSB_D_L<59>
FSB_DSTBN_L<3>
FSB_DSTBP_L<3>
FSB_DINV_L<3>
FSB_LOCK_L
FSB_HIT_L
FSB_HITM_L
FSB_BNR_L
FSB_BREQ0_L
FSB_DBSY_L
FSB_DPWR_L
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_CLK_NB_P
FSB_CLK_NB_N
VR_PWRGOOD_DELAY
NB_RST_IN_L_R
NB_CLK100M_GCLKIN_P
NB_CLK100M_GCLKIN_N
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
PP
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
PP4100
PP4101
1
SM
1
SM
PP
PP
OMIT
P4MM
OMIT
P4MM
NB_FSB_VREF
19 12 6
=PP1V05_S0_FSB_NB
PP1201
1
SM-TP50-TOP
PP3V3_S5
PP5V_S5
PP12V_S5
PP1V8_S3
PPVCORE_CPU
PP3V3_S5_SB_RTC
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
SMC_TRST_L
SMC_TX_L
SMC_RX_L
SMC_MANUAL_RST_L
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
PP1202
1
SM-TP50-TOP
8 TESTPOINTS
FUNC_TEST=TRUE
60 59 58
59
11 7
PLACE NEAR R0705 AND R0706
11 9 8 7 6
11 7
11 7
11 7
=PP1V05_S0_CPU
PP700
1
A
SM-TP50-TOP
PP702
1
A
SM-TP50-TOP
PLACE NEAR R2800 AND R2801
29 28 6
=PP1V8_S3_MEM
PP2800
1
A
A
A
SM-TP50-TOP
34 12
34 12
OMIT
P4MM
OMIT
P4MM
75 26 14
C
34 21
34 21
38 21
38 21
38 21
LAYOUT NOTE: PLACE NEAR U2100
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
IDE_PDIOR_L
IDE_PDIORDY
IDE_PDD<9>
14
OMIT
P4MM
OMIT
P4MM
PP6C4
PP6C5
PP6C6
PP6C7
PP6C8
PP6D0
PP6D1
PP6D2
PP5E1
PP5E2
PP6D3
PP6D4
PP6D5
PP6D6
PP6D7
PP6D8
PP6D9
PP6E0
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
OMIT
P4MM
OMIT
P4MM
34 14
34 14
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
34 14
34 14
NB_CLK_DREFSSCLKIN_P
PP669
NB_CLK_DREFSSCLKIN_N
PP670
NB_CLK_DREFCLKIN_P
NB_CLK_DREFCLKIN_N
OMIT
P4MM
OMIT
P4MM
34 14
34 14
34 22
PP671
PP672
PP673
PP674
PP6E1
PP675
PP676
PP677
PP678
PP679
PP680
PP681
PP682
PP683
PP684
PP685
PP686
PP687
PP688
PP689
PP690
PP691
PP692
PP693
PP694
PP695
PP696
PP697
PP698
PP699
PP6A0
PP6A1
PP6A2
PP6A3
PP6A4
PP6A5
PP6A6
PP6A7
PP6A8
PP6A9
PP6B0
PP6B1
PP6B2
PP6B3
PP6B4
PP6B5
PP6B6
PP6B7
PP6B8
PP6B9
PP6C0
PP6C1
PP6C2
PP6C3
OMIT
P4MM
OMIT
P4MM
PCI_CLK_SB
PCIE_A_D2R_P
PCIE_A_D2R_N
PCIE_B_D2R_P
PCIE_B_D2R_N
DMI_N2S_P<0>
DMI_N2S_N<0>
SB_CLK100M_DMI_P
SB_CLK100M_DMI_N
PM_SYSRST_L
PM_CLKRUN_L
SB_CLK14P3M_TIMER
SB_CLK48M_USBCTLR
1
SM PP
1
SM PP
1
SM PP
1
SM
1
SM
PP
PP
OMIT
P4MM
22 14
22 14
54 22
54 22
OMIT
P4MM
OMIT
P4MM
DMI_S2N_N<0>
DMI_S2N_P<0>
MEM_VREF_NB_0
MEM_VREF_NB_1
MEM_A_DQ<7>
MEM_A_DQ<14>
MEM_A_DQ<16>
MEM_A_DQ<25>
MEM_A_DQ<39>
MEM_A_DQ<47>
MEM_A_DQ<54>
MEM_A_DQ<59>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_DQ<6>
MEM_B_DQ<8>
MEM_B_DQ<23>
MEM_B_DQ<25>
MEM_B_DQ<38>
MEM_B_DQ<44>
MEM_B_DQ<48>
MEM_B_DQ<62>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
1
SM
PP
1
SM PP
OMIT
P4MM
OMIT
P4MM
54 22
54 22
OMIT
P4MM
OMIT
P4MM
19 14
19 14
28 15
28 15
28 15
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
1
SM
PP
PP
22 14
22 14
1
SM PP
1
SM PP
1
SM PP
1
SM
PP
1
SM
PP
OMIT
P4MM
OMIT
P4MM
34 22
34 22
OMIT
P4MM
OMIT
P4MM
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
58 26 23
58 44 23
67 60
34 23
34 23
1
SM PP
1
SM PP
1
SM PP
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
B
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
1
SM
PP
PP
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
A
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
P
P4MM
1
SM PP
1
SM
PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
PP
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
13
13
13
13
13
13
13
13
13
13
13
13
e
r
13
13
13
13
13
13
13
13
13
13
13
13
13
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<6>
PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>
NC_PEG_R2D_C_N<4>
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<5>
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<6>
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<7>
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<8>
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<9>
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<10>
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<11>
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<12>
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<13>
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<14>
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<15>
MAKE_BASE=TRUE
NC_PEG_D2R_N<3>
MAKE_BASE=TRUE
NC_PEG_D2R_N<4>
MAKE_BASE=TRUE
NC_PEG_D2R_N<5>
MAKE_BASE=TRUE
NC_PEG_D2R_N<6>
MAKE_BASE=TRUE
NC_PEG_D2R_N<7>
MAKE_BASE=TRUE
NC_PEG_D2R_N<8>
MAKE_BASE=TRUE
NC_PEG_D2R_N<9>
MAKE_BASE=TRUE
NC_PEG_D2R_N<10>
MAKE_BASE=TRUE
NC_PEG_D2R_N<11>
MAKE_BASE=TRUE
NC_PEG_D2R_N<12>
MAKE_BASE=TRUE
NC_PEG_D2R_N<13>
MAKE_BASE=TRUE
NC_PEG_D2R_N<14>
MAKE_BASE=TRUE
NC_PEG_D2R_N<15>
MAKE_BASE=TRUE
m
i
l
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
a
n
i
29 28
MEM_VREF
PP2801
1
PP2802
1
SM-TP50-TOP
SM-TP50-TOP
HOLE-VIA
1
ZH599
TP_SLOT
y
r
11 7
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
POWER_BUTTON_L
SW_RST_BTN_L
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
D
59
26
MISC GROUND VIAS
HOLE-VIA
1
ZH500
HOLE-VIA
1
ZH510
ZH511
1
HOLE-VIA
1
ZH520
ZH521
1
HOLE-VIA
1
ZH501
HOLE-VIA
HOLE-VIA
C
THIS TEST POINT USED TO
CONNECT THE SHAPES
AROUND SLOT ON TOP AND
BOTTOM OF THE BOARD.
HOLE-VIA
1
ZH502
HOLE-VIA
1
ZH512
HOLE-VIA
1
ZH522
HOLE-VIA
1
ZH503
HOLE-VIA
1
ZH513
HOLE-VIA
1
ZH523
HOLE-VIA
1
ZH504
HOLE-VIA
1
ZH514
HOLE-VIA
1
ZH524
HOLE-VIA
1
ZH505
HOLE-VIA
1
ZH515
HOLE-VIA
1
ZH525
HOLE-VIA
1
NO_TEST=TRUE
58 22
34
29
29
ZH506
HOLE-VIA
1
ZH516
HOLE-VIA
1
ZH526
IN
IN
IN
IN
SPI_ARB
TP_PCI_CLK_SPARE
TP_MEM_B_A<14>
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
TP_MEM_B_A<15>
HOLE-VIA
1
ZH507
HOLE-VIA
1
ZH517
HOLE-VIA
1
ZH527
B
HOLE-VIA
1
ZH508
HOLE-VIA
1
ZH518
HOLE-VIA
1
ZH528
HOLE-VIA
1
ZH509
HOLE-VIA
1
ZH519
HOLE-VIA
1
ZH529
SPARE USB PORT
22
USB_F_N
USB_F_P
TP_USB_F_N
MAKE_BASE=TRUE
TP_USB_F_P
MAKE_BASE=TRUE
22
13
INVERTER DOES NOT USE THIS SIGNAL
TP_LVDS_BKLTEN
LVDS_BKLTEN
MAKE_BASE=TRUE
FUNC TEST 1 OF 2
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
REV.
A
APPLE COMPUTER INC.
D
SCALE
NONE
051-7199
SHT
A
97
5
OF
8
7
6
5
4
3
2
1

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